4.18.5. Debug features

The ARM926CT component exports a CADI debug interface.


All processor, CP15 registers are visible in the debugger. See the processor technical reference manual for a detailed description of available registers.

The CP14 DSCR register is visible for compatibility reasons with some debuggers. This register has no defined behavior.


There is direct support for:

  • single unconditional instruction breakpoints

  • unconditional instruction range breakpoints

  • single unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints. The current models do not support processor exception breakpoints.

The current models support processor exception breakpoints by the use of pseudoregisters available in the debugger register window. When debugger support is added to directly support processor exceptions, these pseudoregisters are removed.

Setting an exception register to a nonzero value causes execution to stop on entry to the associated exception vector.


The ARM926CT component presents a single flat 4GB view of virtual memory as seen by the model processor.

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