6.5.1. Ports

Table 6.10 provides a brief description of the VE_SysRegs component ports. For more information, see the hardware documentation.

Table 6.10. VE_SysRegs ports

NamePort ProtocolTypeDescription
cb[0-1]VECBProtocolmasterThe Configuration Bus (CB) controls the power and reset sequence.
clk_24MhzClockSignalslaveReference clock for internal counter register.
clk_100HzClockSignalslaveReference clock for internal counter register.
clock_CLCDClockRate ControlmasterThe clock for the LCD controller.
lcdLCDmasterMulti-media bus interface output to the LCD.
ledsValueStatemasterDisplays state of the SYS_LED register using the eight colored LEDs on the status bar.
mmb[0-2]LCDslaveMulti-media bus interface input.
mmc_card_presentStateSignalslaveIndicates if an image representing an MultiMedia Card (MMC) has been configured.
pvbusPVBusslaveSlave port for connection to PV bus master/decoder.
user_switches ValueStatemasterProvides state for the eight User DIP switches on the left side of the CLCD status bar, equivalent to switch S6 on VE hardware.

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