7.5.1. Ports

Table 7.8 provides a brief description of the EB_SysRegs component ports. For more information, see the hardware documentation.

Table 7.8. EB_SysRegs ports

NamePort ProtocolTypeDescription
pvbusPVBusslaveslave port for connection to PV bus master/decoder
clk_in_24mhzClockSignalslavereference clock for internal counter register
clk_in_100hzClockSignalslavereference clock for internal counter register
osc0ICS307Configurationmastersettings for the ICS307 OSC0
osc1ICS307Configurationmastersettings for the ICS307 OSC1
osc2ICS307Configurationmastersettings for the ICS307 OSC2
osc3ICS307Configurationmastersettings for the ICS307 OSC4
osc4ICS307Configurationmastersettings for the ICS307 OSC5
boot_control ValueStatemasterpasses the value of the boot switch to the EBRemapper component[a]
boot_switch ValueStatemasterprovides state for the eight Boot DIP switches on the right side of the CLCD status bar, equivalent to switch S8 on EB hardware
ledsValueStatemasterdisplays state of the SYS_LED register using the eight colored LEDs on the status bar
user_switches ValueStatemasterprovides state for the eight User DIP switches on the left side of the CLCD status bar, equivalent to switch S6 on EB hardware.

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