8.2.1. MPS registers

This section describes the MPS memory-mapped registers.

Processor system registers

Table 8.2 provides a description of the processor system registers.

Table 8.2. MPS processor system registers

Register nameAddressAccessDescription
SYS_ID0x1F000000read/writeBoard and FPGA identifier
SYS_MEMCFG0x1F000004read/writeMemory remap and alias
SYS_SW0x1F000008read/writeIndicates user switch settings
SYS_LED0x1F00000Cread/writeSets LED outputs
SYS_TS0x1F000010read/writeTouchScreen register

DUT system registers

Table 8.15 provides a description of the DUT system registers.

Table 8.3. MPS DUT system registers

Register nameAddressAccessDescription
SYS_ID0x40004000read/writeBoard and FPGA identifier
SYS_PERCFG0x40004004read/writePeripheral control signals
SYS_SW0x40004008read/writeIndicates user switch settings
SYS_LED0x4000400Cread/writeSets LED outputs
SYS_7SEG0x40004010read/writeSets seven-segment LED outputs
SYS_CNT25MHZ0x40004014read/writeFree running counter incrementing at 25MHz
SYS_CNT100HZ0x40004018read/writeFree running counter incrementing at 100Hz

Character LCD registers

Table 8.12 provides a description of the character LCD registers.

Table 8.4. MPS LCD registers

Register nameAddressAccessDescription
CHAR_COM0x4000C000writeCommand register. The command set is compatible with the commands of the Hitachi HD44780U controller.
CHAR_DAT0x4000C004writeWrite data register.
CHAR_RD0x4000C008readRead data register.
CHAR_RAW0x4000C00Cread/writeRaw interrupt.
CHAR_MASK0x4000C010read/writeInterrupt mask.
CHAR_STAT0x4000C014read/writeMasked interrupt.

Memory configuration and remap

Table 8.5 provides a description of the memory configuration register.

Table 8.5. Memory configuration

NameBitsAccessPower On ResetDescription
Reserved31:3---
SWDPEN2RW0bSingle Wire Debug Port Enable. 1 is SWD 0 JTAG
ALIAS1RW1bAlias FLASH. 1 is Aliased on. 0 is Aliased off
REMAP0RW0bRemap SSRAM. 1 is Remap on. 0 is Remap off

The ability to remap the Static memory into the bottom of memory (overlaying the Flash) is required for booting and code execution to permit the interrupt vector table to be modified. It is also used to permit boot code execution from SRAM for code development, rather than programming the FLASH each time.

The aliasing of the Flash memory into SRAM space is required to permit the Flash memory to be reprogrammed at this offset. It also permits full flash memory access when the Remap is enabled, otherwise only the Flash memory above 4MB would be accessible.

Switches

Table 8.6 lists the bits for the user switch inputs.

Table 8.6. User switches

NameBitsAccessResetNote
Reserved31:8---
USER_BUT[3:0]7:4RO-Always returns value of user buttons
USER_SW[3:0]3:0RO-Always returns value of user switches

Seven-segment display

Table 8.7 lists the bits that control the seven-segment display.

Table 8.7. Seven-segment register

NameBitsAccessResetNote
DISP331:24RW0x00Segments for display 3
DISP223:16RW0x00Segments for display 2
DISP115:8RW0x00Segments for display 1
DISP07:0RW0x00Segments for display 0

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