8.5.1. Ports

Table 8.13 provides a brief description of the ports of the MPS_DUTSysReg component. For more information, see the Microcontroller Prototyping System hardware documentation.

Table 8.13. MPS_DUTSysReg ports

NamePort protocolTypeDescription
pvbusPVBusslaveFor connection to PV bus master/decoder.
clk_in_25mhzClockSignalslaveReference clock for internal counterregister.
clk_in_100hzClockSignalslaveReference clock for internal counterregister.
percfgValueStatemasterStatus of SD card.
user_switchesValueStatemasterStatus of user switches.
ledsValueStatemasterStatus of LEDs.
leds_7segValueStatemasterStatus of seven segment display.

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