Fast Models Reference Manual

Version 8.4


Table of Contents

Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Other information
1 Introduction to the Fast Models Reference Manual
1.1 About the components
2 Accuracy and Functionality in Fast Models
2.1 Model capabilities
2.2 Functional caches in Fast Models
2.2.1 Functional caches in Fast Models - about
2.2.2 Functional caches in Fast Models - performance
2.3 Fast Models accuracy
2.3.1 How accurate are Fast Models?
2.3.2 Timing accuracy of Fast Models
2.3.3 Bus traffic in Fast Models
2.3.4 Instruction prefetch in Fast Models
2.3.5 Out-of-order execution and write-buffers in Fast Models
2.3.6 Caches in Fast Models
3 Framework Protocols in Fast Models
3.1 Framework and protocols - about
3.2 Signaling protocols
3.2.1 Signaling protocols - about
3.2.2 Signal protocol
3.2.3 StateSignal protocol
3.2.4 Value protocol
3.2.5 ValueState protocol
3.3 Clocking components and protocols
3.3.1 Clocking components and protocols - about
3.3.2 MasterClock component
3.3.3 ClockDivider component
3.3.4 ClockTimer component
3.3.5 ClockTimer64 component
3.4 Debug interface protocols
3.4.1 Debug interface protocols - about
3.4.2 CADIProtocol protocol
3.4.3 CADIDisassemblerProtocol
4 Processor Components in Fast Models
4.1 About the CT processor components
4.2 ARMCortexA57xnCT component
4.2.1 ARMCortexA57xnCT - about
4.2.2 ARMCortexA57xnCT - ports
4.2.3 ARMCortexA57xnCT - additional protocols
4.2.4 ARMCortexA57xnCT - parameters
4.2.5 ARMCortexA57xnCT - registers
4.2.6 ARMCortexA57xnCT - caches
4.2.7 ARMCortexA57xnCT - debug features
4.2.8 ARMCortexA57xnCT - verification and testing
4.2.9 ARMCortexA57xnCT - performance
4.2.10 ARMCortexA57xnCT - library dependencies
4.2.11 ARMCortexA57xnCT - differences between the CT model and RTL implementations
4.3 ARMCortexA53xnCT component
4.3.1 ARMCortexA53xnCT - about
4.3.2 ARMCortexA53xnCT - ports
4.3.3 ARMCortexA53xnCT - additional protocols
4.3.4 ARMCortexA53xnCT - parameters
4.3.5 ARMCortexA53xnCT - registers
4.3.6 ARMCortexA53xnCT - caches
4.3.7 ARMCortexA53xnCT - debug features
4.3.8 ARMCortexA53xnCT - verification and testing
4.3.9 ARMCortexA53xnCT - performance
4.3.10 ARMCortexA53xnCT - library dependencies
4.3.11 ARMCortexA53xnCT - differences between the CT model and RTL implementations
4.4 ARMCortexA15xnCT component
4.4.1 ARMCortexA15xnCT - about
4.4.2 ARMCortexA15xnCT - ports
4.4.3 ARMCortexA15xnCT - additional protocols
4.4.4 ARMCortexA15xnCT - parameters
4.4.5 ARMCortexA15xnCT - registers
4.4.6 ARMCortexA15xnCT - caches
4.4.7 ARMCortexA15xnCT - debug features
4.4.8 ARMCortexA15xnCT - verification and testing
4.4.9 ARMCortexA15xnCT - performance
4.4.10 ARMCortexA15xnCT - library dependencies
4.4.11 ARMCortexA15xnCT - differences between the CT model and RTL implementations
4.5 ARMCortexA12xnCT component
4.5.1 ARMCortexA12xnCT - about
4.5.2 ARMCortexA12xnCT - ports
4.5.3 ARMCortexA12xnCT - additional protocols
4.5.4 ARMCortexA12xnCT - parameters
4.5.5 ARMCortexA12xnCT - registers
4.5.6 ARMCortexA12xnCT - caches
4.5.7 ARMCortexA12xnCT - debug features
4.5.8 ARMCortexA12xnCT - verification and testing
4.5.9 ARMCortexA12xnCT - performance
4.5.10 ARMCortexA12xnCT - library dependencies
4.5.11 ARMCortexA12xnCT - differences between the CT model and RTL implementations
4.6 ARMCortexA9MPxnCT component
4.6.1 ARMCortexA9MPxnCT - about
4.6.2 ARMCortexA9MPxnCT - ports
4.6.3 ARMCortexA9MPxnCT - additional protocols
4.6.4 ARMCortexA9MPxnCT - parameters
4.6.5 ARMCortexA9MPxnCT - registers
4.6.6 ARMCortexA9MPxnCT - caches
4.6.7 ARMCortexA9MPxnCT - debug features
4.6.8 ARMCortexA9MPxnCT - verification and testing
4.6.9 ARMCortexA9MPxnCT - performance
4.6.10 ARMCortexA9MPxnCT - library dependencies
4.6.11 ARMCortexA9MPxnCT - differences between the CT model and RTL implementations
4.7 ARMCortexA9UPCT component
4.7.1 ARMCortexA9UPCT - about
4.7.2 ARMCortexA9UPCT - ports
4.7.3 ARMCortexA9UPCT - additional protocols
4.7.4 ARMCortexA9UPCT - parameters
4.7.5 ARMCortexA9UPCT - registers
4.7.6 ARMCortexA9UPCT - caches
4.7.7 ARMCortexA9UPCT - debug features
4.7.8 ARMCortexA9UPCT - verification and testing
4.7.9 ARMCortexA9UPCT - performance
4.7.10 ARMCortexA9UPCT - library dependencies
4.7.11 ARMCortexA9UPCT - differences between the CT model and RTL implementations
4.8 ARMCortexA8CT component
4.8.1 ARMCortexA8CT - about
4.8.2 ARMCortexA8CT - ports
4.8.3 ARMCortexA8CT - additional protocols
4.8.4 ARMCortexA8CT - parameters
4.8.5 ARMCortexA8CT - registers
4.8.6 ARMCortexA8CT - caches
4.8.7 ARMCortexA8CT - debug features
4.8.8 ARMCortexA8CT - verification and testing
4.8.9 ARMCortexA8CT - performance
4.8.10 ARMCortexA8CT - library dependencies
4.8.11 ARMCortexA8CT - differences between the CT model and RTL implementations
4.9 ARMCortexA7xnCT component
4.9.1 ARMCortexA7xnCT - about
4.9.2 ARMCortexA7xnCT - ports
4.9.3 ARMCortexA7xnCT - additional protocols
4.9.4 ARMCortexA7xnCT - parameters
4.9.5 ARMCortexA7xnCT - registers
4.9.6 ARMCortexA7xnCT - caches
4.9.7 ARMCortexA7xnCT - debug features
4.9.8 ARMCortexA7xnCT - verification and testing
4.9.9 ARMCortexA7xnCT - performance
4.9.10 ARMCortexA7xnCT - library dependencies
4.9.11 ARMCortexA7xnCT - differences between the CT model and RTL implementations
4.10 ARMCortexA5MPxnCT component
4.10.1 ARMCortexA5MPxnCT - about
4.10.2 ARMCortexA5MPxnCT - ports
4.10.3 ARMCortexA5MPxnCT - additional protocols
4.10.4 ARMCortexA5MPxnCT - parameters
4.10.5 ARMCortexA5MPxnCT - registers
4.10.6 ARMCortexA5MPxnCT - caches
4.10.7 ARMCortexA5MPxnCT - debug features
4.10.8 ARMCortexA5MPxnCT - verification and testing
4.10.9 ARMCortexA5MPxnCT - performance
4.10.10 ARMCortexA5MPxnCT - library dependencies
4.10.11 ARMCortexA5MPxnCT - differences between the CT model and RTL implementations
4.11 ARMCortexA5CT component
4.11.1 ARMCortexA5CT - about
4.11.2 ARMCortexA5CT - ports
4.11.3 ARMCortexA5CT - additional protocols
4.11.4 ARMCortexA5CT - parameters
4.11.5 ARMCortexA5CT - registers
4.11.6 ARMCortexA5CT - caches
4.11.7 ARMCortexA5CT - debug features
4.11.8 ARMCortexA5CT - verification and testing
4.11.9 ARMCortexA5CT - performance
4.11.10 ARMCortexA5CT - library dependencies
4.11.11 ARMCortexA5CT - differences between the CT model and RTL implementations
4.12 ARMCortexR7MPxnCT component
4.12.1 ARMCortexR7MPxnCT - about
4.12.2 ARMCortexR7MPxnCT - ports
4.12.3 ARMCortexR7MPxnCT - additional protocols
4.12.4 ARMCortexR7MPxnCT - parameters
4.12.5 ARMCortexR7MPxnCT - registers
4.12.6 ARMCortexR7MPxnCT - caches
4.12.7 ARMCortexR7MPxnCT - debug features
4.12.8 ARMCortexR7MPxnCT - verification and testing
4.12.9 ARMCortexR7MPxnCT - performance
4.12.10 ARMCortexR7MPxnCT - library dependencies
4.12.11 ARMCortexR7MPxnCT - differences between the CT model and RTL implementations
4.13 ARMCortexR5CT component
4.13.1 ARMCortexR5CT - about
4.13.2 ARMCortexR5CT - ports
4.13.3 ARMCortexR5CT - additional protocols
4.13.4 ARMCortexR5CT - parameters
4.13.5 ARMCortexR5CT - registers
4.13.6 ARMCortexR5CT - caches
4.13.7 ARMCortexR5CT - debug features
4.13.8 ARMCortexR5CT - verification and testing
4.13.9 ARMCortexR5CT - performance
4.13.10 ARMCortexR5CT - library dependencies
4.13.11 ARMCortexR5CT - differences between the CT model and RTL implementations
4.14 ARMCortexR4CT component
4.14.1 ARMCortexR4CT - about
4.14.2 ARMCortexR4CT - ports
4.14.3 ARMCortexR4CT - additional protocols
4.14.4 ARMCortexR4CT - parameters
4.14.5 ARMCortexR4CT - registers
4.14.6 ARMCortexR4CT - caches
4.14.7 ARMCortexR4CT - debug features
4.14.8 ARMCortexR4CT - verification and testing
4.14.9 ARMCortexR4CT - performance
4.14.10 ARMCortexR4CT - library dependencies
4.14.11 ARMCortexR4CT - differences between the CT model and RTL implementations
4.15 ARMCortexM4CT component
4.15.1 ARMCortexM4CT - about
4.15.2 ARMCortexM4CT - ports
4.15.3 ARMCortexM4CT - additional protocols
4.15.4 ARMCortexM4CT - parameters
4.15.5 ARMCortexM4CT - registers
4.15.6 ARMCortexM4CT - caches
4.15.7 ARMCortexM4CT - debug features
4.15.8 ARMCortexM4CT - verification and testing
4.15.9 ARMCortexM4CT - performance
4.15.10 ARMCortexM4CT - library dependencies
4.15.11 ARMCortexM4CT - differences between the CT model and RTL implementations
4.16 ARMCortexM3CT component
4.16.1 ARMCortexM3CT - about
4.16.2 ARMCortexM3CT - ports
4.16.3 ARMCortexM3CT - additional protocols
4.16.4 ARMCortexM3CT - parameters
4.16.5 ARMCortexM3CT - registers
4.16.6 ARMCortexM3CT - caches
4.16.7 ARMCortexM3CT - debug features
4.16.8 ARMCortexM3CT - verification and testing
4.16.9 ARMCortexM3CT - performance
4.16.10 ARMCortexM3CT - library dependencies
4.16.11 ARMCortexM3CT - differences between the CT model and RTL implementations
4.17 ARM1176CT component
4.17.1 ARM1176CT - about
4.17.2 ARM1176CT - ports
4.17.3 ARM1176CT - additional protocols
4.17.4 ARM1176CT - parameters
4.17.5 ARM1176CT - registers
4.17.6 ARM1176CT - debug features
4.17.7 ARM1176CT - verification and testing
4.17.8 ARM1176CT - performance
4.17.9 ARM1176CT - library dependencies
4.17.10 ARM1176CT - differences between the CT model and RTL implementations
4.18 ARM1136CT component
4.18.1 ARM1136CT - about
4.18.2 ARM1136CT - ports
4.18.3 ARM1136CT - additional protocols
4.18.4 ARM1136CT - parameters
4.18.5 ARM1136CT - registers
4.18.6 ARM1136CT - debug features
4.18.7 ARM1136CT - verification and testing
4.18.8 ARM1136CT - performance
4.18.9 ARM1136CT - library dependencies
4.18.10 ARM1136CT - differences between the CT model and RTL implementations
4.19 ARM968CT component
4.19.1 ARM968CT - about
4.19.2 ARM968CT - ports
4.19.3 ARM968CT - additional protocols
4.19.4 ARM968CT - parameters
4.19.5 ARM968CT - registers
4.19.6 ARM968CT - debug features
4.19.7 ARM968CT - verification and testing
4.19.8 ARM968CT - performance
4.19.9 ARM968CT - library dependencies
4.19.10 ARM968CT - DMA
4.20 ARM926CT component
4.20.1 ARM926CT - about
4.20.2 ARM926CT - ports
4.20.3 ARM926CT - additional protocols
4.20.4 ARM926CT - parameters
4.20.5 ARM926CT - registers
4.20.6 ARM926CT - debug features
4.20.7 ARM926CT - verification and testing
4.20.8 ARM926CT - performance
4.20.9 ARM926CT - library dependencies
4.20.10 ARM926CT - differences between the CT model and RTL implementations
4.21 Implementation differences
4.21.1 Caches in PV models
4.21.2 CP14 Debug coprocessor
4.21.3 MicroTLB
4.21.4 TLBs in PV models
4.21.5 Memory access in PV models
4.21.6 Timing in PV models
4.21.7 VIC port in PV models
4.22 Processor CADI implementation of optional functionality
4.22.1 CADI implementation
4.23 CADI interactions with processor behavior
4.24 Additional protocols
4.24.1 CounterInterface protocol
4.24.2 GICv3Comms protocol
4.24.3 InstructionCount protocol
4.24.4 v8EmbeddedCrossTrigger_controlprotocol protocol
5 Peripheral and Interface Components in Fast Models
5.1 About the PV peripheral and interface components
5.2 PVBus components
5.2.1 About PVBus components
5.2.2 About PVBus system components
5.2.3 PVBus Transaction Master ID
5.2.4 PVBus examples
5.2.5 PVBusDecoder component
5.2.6 PVBusMaster component
5.2.7 PVBusRange component
5.2.8 PVBusSlave component
5.2.9 TZSwitch component
5.2.10 PVBus labeller components
5.2.11 PVBus C++ transaction and Tx_Result classes
5.3 AMBA-PV components
5.3.1 About the AMBA-PV components
5.3.2 AMBA-PV component protocols
5.3.3 PVBus2AMBAPV component
5.3.4 AMBAPV2PVBus component
5.3.5 PVBus2AMBAPVACE component
5.3.6 AMBAPVACE2PVBus component
5.3.7 SGSignal2AMBAPVSignal component
5.3.8 AMBAPVSignal2SGSignal component
5.3.9 SGStateSignal2AMBAPVSignalState component
5.3.10 AMBAPVSignalState2SGStateSignal component
5.3.11 SGValue2AMBAPVValue component
5.3.12 SGValue2AMBAPVValue64 component
5.3.13 AMBAPVValue2SGValue component
5.3.14 AMBAPVValue2SGValue64 component
5.3.15 SGValueState2AMBAPVValueState component
5.3.16 SGValueState2AMBAPVValueState64 component
5.3.17 AMBAPVValueState2SGValueState component
5.3.18 AMBAPVValueState2SGValueState64 component
5.4 Example Peripheral Components
5.4.1 About the Example Peripheral Components Model Library
5.4.2 PL011_Uart component
5.4.3 SerialCrossover component
5.4.4 TelnetTerminal component
5.4.5 PL022_SSP component
5.4.6 PL030_RTC component
5.4.7 PL031_RTC component
5.4.8 PL041_AACI component
5.4.9 AudioOut_File component
5.4.10 AudioOut_SDL component
5.4.11 PL050_KMI component
5.4.12 PS2Keyboard component
5.4.13 PS2Mouse component
5.4.14 PL061_GPIO component
5.4.15 PL080_DMAC component
5.4.16 PL110_CLCD component
5.4.17 PL111_CLCD component
5.4.18 PL180_MCI component
5.4.19 MMC component
5.4.20 PL192_VIC component
5.4.21 PL310_L2CC component
5.4.22 PL330_DMAC component
5.4.23 PL340_DMC component
5.4.24 PL350_SMC component
5.4.25 PL350_SMC_NAND_FLASH component
5.4.26 PL390_GIC component
5.4.27 SP804_Timer component
5.4.28 SP805_Watchdog component
5.4.29 SP810_SysCtrl component
5.4.30 TZIC component
5.4.31 RemapDecoder component
5.4.32 BP135_AXI2APB component
5.4.33 BP141_TZMA component
5.4.34 BP147_TZPC component
5.4.35 AndGate component
5.4.36 OrGate component
5.4.37 ICS307 component
5.4.38 ElfLoader component
5.4.39 FlashLoader component
5.4.40 IntelStrataFlashJ3 component
5.4.41 VFS2 component
5.4.42 MessageBox component
5.4.43 RAMDevice component
5.4.44 SMSC_91C111 component
5.4.45 HostBridge component
5.4.46 VirtualEthernetCrossover component
5.4.47 CCI400 component
5.4.48 DMC_400 component
5.4.49 GIC_400 component
5.4.50 MMU_400 component
5.4.51 TZC_400 component
5.4.52 MemoryMappedCounterModule component
5.4.53 v8EmbeddedCrossTrigger_Interface component
5.4.54 v8EmbeddedCrossTrigger_Matrix component
5.5 Visualisation Library
5.5.1 Visualisation Library - about
5.5.2 LCD protocol
5.5.3 LISA Visualisation models
5.5.4 GUIPoll component
5.5.5 Visualisation Library C++ classes
5.6 Using component features
5.6.1 Terminal
5.6.2 Setting up and using user mode networking
5.6.3 Set-up of a TAP network connection and configuration of the networking environment for Microsoft Windows
5.6.4 Set-up of a network connection and configuration of the networking environment for Linux
5.7 CADI sync watchpoints
5.8 Non-CADI sync watchpoints
5.8.1 syncLevel definitions
5.8.2 Controlling and observing the syncLevel
5.9 SCADI
5.9.1 About SCADI
5.9.2 Intended uses of CADI and SCADI
5.9.3 Responsibilities of the SCADI caller
5.9.4 SCADI interface access
5.9.5 SCADI semantics
6 AEMv8-A Base Platform: Platform and Components
6.1 About the AEMv8-A Base Platform
6.2 AEMv8-A Base Platform - Virtual File System
6.3 AEMv8-A Base Platform - memory
6.3.1 AEMv8-A Base Platform - memory - security
6.3.2 AEMv8-A Base Platform - memory - map
6.3.3 AEMv8-A Base Platform - memory - DRAM
6.4 AEMv8-A Base Platform - interrupt assignments
6.5 AEMv8-A Base Platform - clocks
6.6 AEMv8-A Base Platform - components
6.6.1 AEMv8-A Base Platform - components - about
6.6.2 AEMv8-A Base Platform - AEMv8-A processor and platform
6.6.3 AEMv8-A Base Platform - Generic Timer
6.6.4 AEMv8-A Base Platform - TZC-400
6.6.5 AEMv8-A Base Platform - watchdogs
6.6.6 AEMv8-A Base Platform - CCI-400
6.6.7 AEMv8-A Base Platform - GICv3
6.6.8 AEMv8-A Base Platform - power controller
6.6.9 AEMv8-A Base Platform - virtio block device
6.6.10 AEMv8-A Base Platform - simulator
6.6.11 AEMv8-A Base Platform - UART
6.6.12 AEMv8-A Base Platform - flash
6.6.13 AEMv8-A Base Platform - networking
6.6.14 AEMv8-A Base Platform - MMC device
6.6.15 AEMv8-A Base Platform - simulator visualization
6.6.16 AEMv8-A Base Platform - other components
6.7 AEMv8-A Base Platform - VE compatibility
6.7.1 AEMv8-A Base Platform - VE compatibility - GICv2
6.7.2 AEMv8-A Base Platform - VE compatibility - GICv3
6.7.3 AEMv8-A Base Platform - VE compatibility - system global counter
6.7.4 AEMv8-A Base Platform - VE compatibility - disable security
6.8 AEMv8-A Base Platform - unsupported VE features
6.8.1 AEMv8-A Base Platform - unsupported VE features - memory aliasing at 0x08_00000000
6.8.2 AEMv8-A Base Platform - unsupported VE features - boot ROM alias at 0x00_0800_0000
6.8.3 AEMv8-A Base Platform - unsupported VE features - change of older parameters
7 Versatile Express Model: Platform and Components
7.1 About the Versatile Express baseboard components
7.2 VE memory map for Cortex-A series
7.3 VE memory map for Cortex-R series
7.4 VE parameters
7.4.1 VE instantiation syntax and parameters
7.4.2 VE secure memory parameters
7.4.3 VE switch S6
7.5 VEVisualisation component
7.5.1 VEVisualisation - about
7.5.2 VEVisualisation - ports
7.5.3 VEVisualisation - additional protocols
7.5.4 VEVisualisation - parameters
7.5.5 VEVisualisation - registers
7.5.6 VEVisualisation - debug features
7.5.7 VEVisualisation - verification and testing
7.5.8 VEVisualisation - performance
7.5.9 VEVisualisation - library dependencies
7.6 VE_SysRegs component
7.6.1 VE_SysRegs - about
7.6.2 VE_SysRegs - ports
7.6.3 VE_SysRegs - additional protocols
7.6.4 VE_SysRegs - parameters
7.6.5 VE_SysRegs - registers
7.6.6 VE_SysRegs - debug features
7.6.7 VE_SysRegs - verification and testing
7.6.8 VE_SysRegs - performance
7.6.9 VE_SysRegs - library dependencies
7.7 Other VE components
7.7.1 VEConnector and VESocket components
7.7.2 VEInterruptForwarder component
7.7.3 VERemapper component
7.8 Differences between the VE hardware and the system model
7.8.1 Memory map
7.8.2 Memory aliasing
7.8.3 VE hardware features absent
7.8.4 VE hardware features different
7.8.5 Restrictions on the processor models
7.8.6 Timing considerations for the VE FVPs
8 Emulation Baseboard Model: Platform and Components
8.1 About the Emulation Baseboard components
8.2 EB memory map
8.3 EB parameters
8.3.1 EB instantiation syntax and parameters
8.3.2 EB switch S6
8.3.3 EB switch S8
8.4 EBVisualisation component
8.4.1 EBVisualisation - about
8.4.2 EBVisualisation - ports
8.4.3 EBVisualisation - additional protocols
8.4.4 EBVisualisation - parameters
8.4.5 EBVisualisation - registers
8.4.6 EBVisualisation - debug features
8.4.7 EBVisualisation - verification and testing
8.4.8 EBVisualisation - performance
8.4.9 EBVisualisation - library dependencies
8.5 EB_SysRegs component
8.5.1 EB_SysRegs - about
8.5.2 EB_SysRegs - ports
8.5.3 EB_SysRegs - additional protocols
8.5.4 EB_SysRegs - parameters
8.5.5 EB_SysRegs - registers
8.5.6 EB_SysRegs - debug features
8.5.7 EB_SysRegs - verification and testing
8.5.8 EB_SysRegs - performance
8.5.9 EB_SysRegs - library dependencies
8.6 EBCortexA9_SysRegs component
8.6.1 EBCortexA9_SysRegs - about
8.6.2 EBCortexA9_SysRegs - ports
8.6.3 EBCortexA9_SysRegs - additional protocols
8.6.4 EBCortexA9_SysRegs - parameters
8.6.5 EBCortexA9_SysRegs - registers
8.6.6 EBCortexA9_SysRegs - debug features
8.6.7 EBCortexA9_SysRegs - verification and testing
8.6.8 EBCortexA9_SysRegs - performance
8.6.9 EBCortexA9_SysRegs - library dependencies
8.7 TSC2200 component
8.7.1 TSC2200 - about
8.7.2 TSC2200 - ports
8.7.3 TSC2200 - additional protocols
8.7.4 TSC2200 - parameters
8.7.5 TSC2200 - registers
8.7.6 TSC2200 - debug features
8.7.7 TSC2200 - verification and testing
8.7.8 TSC2200 - performance
8.7.9 TSC2200 - library dependencies
8.7.10 TSC2200 - functionality
8.8 Other EB components
8.8.1 EBConnector and EBSocket components
8.8.2 EBInterruptForwarder component
8.8.3 EBRemapper component
8.9 Differences between the EB hardware and the system model
8.9.1 EB hardware features absent
8.9.2 EB hardware features different
8.9.3 Remapping and DRAM aliasing
8.9.4 Dynamic memory characteristics
8.9.5 Status and system control registers
8.9.6 EB FVP PrimeCell Generic Interrupt Controller (PL390)
8.9.7 GPIO2
8.9.8 Timing considerations for the EB FVPs
9 Microcontroller Prototyping System: Platform and Components
9.1 About the Microcontroller Prototyping System components
9.2 MPS memory map
9.2.1 Overview of MPS memory map
9.2.2 MPS registers
9.3 MPSVisualisation component
9.3.1 MPSVisualisation - about
9.3.2 MPSVisualisation - ports
9.3.3 MPSVisualisation - additional protocols
9.3.4 MPSVisualisation - parameters
9.3.5 MPSVisualisation - registers
9.3.6 MPSVisualisation - debug features
9.3.7 MPSVisualisation - verification and testing
9.3.8 MPSVisualisation - performance
9.3.9 MPSVisualisation - library dependencies
9.4 MPS_CharacterLCD component
9.4.1 MPS_CharacterLCD - about
9.4.2 MPS_CharacterLCD - ports
9.4.3 MPS_CharacterLCD - additional protocols
9.4.4 MPS_CharacterLCD - parameters
9.4.5 MPS_CharacterLCD - registers
9.4.6 MPS_CharacterLCD - debug features
9.4.7 MPS_CharacterLCD - verification and testing
9.4.8 MPS_CharacterLCD - performance
9.4.9 MPS_CharacterLCD - library dependencies
9.5 MPS_DUTSysReg component
9.5.1 MPS_DUTSysReg - about
9.5.2 MPS_DUTSysReg - ports
9.5.3 MPS_DUTSysReg - additional protocols
9.5.4 MPS_DUTSysReg - parameters
9.5.5 MPS_DUTSysReg - registers
9.5.6 MPS_DUTSysReg - debug features
9.5.7 MPS_DUTSysReg - verification and testing
9.5.8 MPS_DUTSysReg - performance
9.5.9 MPS_DUTSysReg - library dependencies
9.6 Other MPS components
9.6.1 MPSInterruptForwarder and MPSInterruptReceiver components
9.7 Differences between the MPS hardware and the system model
9.7.1 MPS hardware features different
9.7.2 Timing considerations for the MPS FVPs

List of Figures

3-1 MasterClock in System Canvas
3-2 ClockDivider in System Canvas
3-3 ClockTimer in System Canvas
3-4 ClockTimer64 in System Canvas
4-1 ARMCortexA57x4CT in System Canvas with all vectored ports collapsed
4-2 ARMCortexA53x4CT in System Canvas with all vectored ports collapsed
4-3 ARMCortexA15x4CT in System Canvas with all vectored ports collapsed
4-4 ARMCortexA12x4CT in System Canvas with all vectored ports collapsed
4-5 ARMCortexA9MPx4CT in System Canvas with all vectored ports collapsed
4-6 ARMCortexA9UPCT in System Canvas
4-7 ARMCortexA8CT in System Canvas
4-8 ARMCortexA7x1CT in System Canvas with all vectored ports collapsed
4-9 ARMCortexA5MPCT in System Canvas with all vectored ports collapsed
4-10 ARMCortexA5CT in System Canvas
4-11 ARMCortexR7MPCT in System Canvas with all vectored ports collapsed
4-12 ARMCortexR5CT in System Canvas with all vectored ports collapsed
4-13 ARMCortexR4CT in System Canvas
4-14 ARMCortexM4CT in System Canvas
4-15 ARMCortexM3CT in System Canvas
4-16 ARM1176CT in System Canvas
4-17 ARM1136CT in System Canvas
4-18 ARM968CT in System Canvas
4-19 ARM926CT in System Canvas
5-1 Sample bus topology
5-2 PVBusDecoder in System Canvas
5-3 PVBusMaster in System Canvas
5-4 PVBusRange in System Canvas
5-5 PVBusSlave in System Canvas
5-6 TZSwitch in System Canvas
5-7 Labeller in System Canvas
5-8 LabellerForDMA330 in System Canvas
5-9 PVBus2AMBAPV in System Canvas
5-10 AMBAPV2PVBus in System Canvas
5-11 PVBus2AMBAPVACE in System Canvas
5-12 AMBAPVACE2PVBus in System Canvas
5-13 SGSignal2AMBAPVSignal in System Canvas
5-14 AMBAPVSignal2SGSignal in System Canvas
5-15 SGStateSignal2AMBAPVSignalState in System Canvas
5-16 AMBAPVSignalState2SGStateSignal in System Canvas
5-17 SGValue2AMBAPVValue in System Canvas
5-18 SGValue2AMBAPVValue64 in System Canvas
5-19 AMBAPVValue2SGValue in System Canvas
5-20 AMBAPVValue2SGValue64 in System Canvas
5-21 SGValueState2AMBAPVValueState in System Canvas
5-22 SGValueState2AMBAPVValueState64 in System Canvas
5-23 AMBAPVValueState2SGValueState in System Canvas
5-24 AMBAPVValueState2SGValueState64 in System Canvas
5-25 PL011_Uart in System Canvas
5-26 SerialCrossover in System Canvas
5-27 TelnetTerminal in System Canvas
5-28 PL022_SSP in System Canvas
5-29 PL030_RTC in System Canvas
5-30 PL031_RTC in System Canvas
5-31 PL041_AACI in System Canvas
5-32 AudioOut_File in System Canvas
5-33 AudioOut_SDL in System Canvas
5-34 Keyboard/Mouse controller in System Canvas
5-35 PS2Keyboard in System Canvas
5-36 PS2Mouse component in System Canvas
5-37 PL061_GPIO in System Canvas
5-38 PL080_DMAC in System Canvas
5-39 PL110_CLCD in System Canvas
5-40 PL111_CLCD in System Canvas
5-41 PL180_MCI in System Canvas
5-42 MMC in System Canvas
5-43 PL192_VIC in System Canvas
5-44 PL310_L2CC in System Canvas
5-45 PL310_L2CC in an example system
5-46 PL330_DMAC in System Canvas
5-47 PL340_DMC in System Canvas
5-48 PL350_SMC in System Canvas
5-49 PL350_SMC_NAND_FLASH in System Canvas
5-50 PL390_GIC in System Canvas
5-51 SP804_Timer in System Canvas
5-52 SP805_Watchdog in System Canvas
5-53 SP810_SysCtrl in System Canvas
5-54 TZIC in System Canvas
5-55 RemapDecoder in System Canvas
5-56 BP135_AXI2APB in System Canvas
5-57 BP141_TZMA in System Canvas
5-58 BP147_TZPC in System Canvas
5-59 AndGate in System Canvas
5-60 OrGate in System Canvas
5-61 ICS307 in System Canvas
5-62 ElfLoader in System Canvas
5-63 FlashLoader in System Canvas
5-64 IntelStrataFlashJ3 in System Canvas
5-65 VFS2 in System Canvas
5-66 MessageBox in System Canvas
5-67 RAMDevice in System Canvas
5-68 SMSC_91C111 in System Canvas
5-69 HostBridge in System Canvas
5-70 VirtualEthernetCrossover in System Canvas
5-71 CCI400 in System Canvas
5-72 DMC_400 in System Canvas
5-73 GIC_400 in System Canvas
5-74 MMU_400 in System Canvas
5-75 TZC_400 in System Canvas
5-76 MemoryMappedCounterModule in System Canvas
5-77 v8EmbeddedCrossTrigger_Interface in System Canvas
5-78 v8EmbeddedCrossTrigger_Matrix in System Canvas
5-79 GUIPoll in System Canvas
5-80 Terminal block diagram of one possible relationship between the target and host through the Terminal component
6-1 AEMv8-A Base Platform Power Control Processor Off Register bit assignments
6-2 AEMv8-A Base Platform Power Control Processor On Register bit assignments
6-3 AEMv8-A Base Platform Power Control Cluster Off Register bit assignments
6-4 AEMv8-A Base Platform Power Control Wakeup Register bit assignments
6-5 AEMv8-A Base Platform Power Control SYS Status Register bit assignments
7-1 Startup VE Fixed Virtual Platform CLCD visualization window
7-2 VE FVP CLCD with brot.axf image
7-3 VEVisualisation in System Canvas
7-4 VE_SysRegs in System Canvas
8-1 Startup EB Fixed Virtual Platform CLCD visualization window
8-2 EB FVP CLCD with brot.axf image
8-3 EBVisualisation in System Canvas
8-4 EB_SysRegs in System Canvas
8-5 EBCortexA9_SysRegs in System Canvas
8-6 TSC2200 in System Canvas
9-1 MPSVisualisation component in System Canvas
9-2 Microprocessor Prototyping System Fixed Virtual Platform CLCD
9-3 MPS_CharacterLCD in System Canvas
9-4 MPS_DUTSysReg in System Canvas, with the input ports fully expanded

List of Tables

3-1 MasterClock ports
3-2 ClockDivider ports
3-3 ClockDivider parameters
3-4 ClockTimer ports
3-5 ClockTimer ports
4-1 ARMCortexA57xnCT ports
4-2 ARMCortexA57xnCT parameters
4-3 ARMCortexA53xnCT ports
4-4 ARMCortexA53xnCT parameters
4-5 ARMCortexA15xnCT ports
4-6 ARMCortexA15xnCT cluster parameters
4-7 ARMCortexA15xnCT core parameters
4-8 ARMCortexA12xnCT ports
4-9 ARMCortexA12xnCT parameters
4-10 ARMCortexA9MPxnCT ports
4-11 ARMCortexA9MPxnCT cluster parameters
4-12 ARMCortexA9MPxnCT core parameters
4-13 ARMCortexA9UPCT ports
4-14 ARMCortexA9UPCT cluster parameters
4-15 ARMCortexA9UPCT core parameters
4-16 ARMCortexA8CT ports
4-17 ARMCortexA8CT parameters
4-18 ARMCortexA7xnCT ports
4-19 ARMCortexA7xnCT cluster parameters
4-20 ARMCortexA7xnCT core parameters
4-21 ARMCortexA5MPxnCT ports
4-22 ARMCortexA5MPxnCT cluster parameters
4-23 ARMCortexA5MPxnCT core parameters
4-24 ARMCortexA5CT ports
4-25 ARMCortexA5CT cluster parameters
4-26 ARMCortexA5CT core parameters
4-27 ARMCortexR7MPxnCT ports
4-28 ARMCortexR7MPxnCT cluster parameters
4-29 ARMCortexR7MPxnCT core parameters
4-30 ARMCortexR5CT ports
4-31 ARMCortexR5CT cluster parameters
4-32 ARMCortexR5CT core parameters
4-33 ARMCortexR4CT ports
4-34 ARMCortexR4CT parameters
4-35 ARMCortexM4CT ports
4-36 ARMCortexM4CT parameters
4-37 ARMCortexM3CT ports
4-38 ARMCortexM3CT parameters
4-39 ARM1176CT ports
4-40 ARM1176CT parameters
4-41 ARM1136CT ports
4-42 ARM1136CT parameters
4-43 ARM968CT ports
4-44 ARM968CT parameters
4-45 ARM926CT ports
4-46 ARM926CT parameters
4-47 CADI broker implementation
4-48 CADI target implementation
4-49 Run state values
5-1 PVBus examples
5-2 PVBusDecoder ports
5-3 PVBusMaster ports
5-4 PVBusRange ports
5-5 PVBus ports
5-6 PVBusSlave parameters
5-7 TZSwitch ports
5-8 TZSwitch parameters
5-9 PVBus labeller ports
5-10 PVBus2AMBAPV ports
5-11 PVBus2AMBAPV parameters
5-12 AMBAPV2PVBus ports
5-13 AMBAPV2PVBus parameters
5-14 PVBus2AMBAPVACE ports
5-15 PVBus2AMBAPVACE parameters
5-16 AMBAPVACE2PVBus ports
5-17 SGSignal2AMBAPVSignal ports
5-18 AMBAPVSignal2SGSignal ports
5-19 SGStateSignal2AMBAPVSignalState ports
5-20 AMBAPVSignalState2SGStateSignal ports
5-21 SGValue2AMBAPVValue ports
5-22 SGValue2AMBAPVValue64 ports
5-23 AMBAPVValue2SGValue ports
5-24 AMBAPVValue2SGValue64 ports
5-25 SGValueState2AMBAPVValueState ports
5-26 SGValueState2AMBAPVValueState64 ports
5-27 AMBAPVValueState2SGValueState ports
5-28 AMBAPVValueState2SGValueState64 ports
5-29 PL011_Uart ports
5-30 Bits for dataTransmit()
5-31 Bits for dataReceive()
5-32 Bits for signalsSet()
5-33 Bits for signalsGet()
5-34 PL011_Uart parameters
5-35 PL011_Uart registers
5-36 SerialCrossover ports
5-37 TelnetTerminal ports
5-38 TelnetTerminal parameters
5-39 PL022_SSP ports
5-40 PL022_SSP registers
5-41 PL030_RTC ports
5-42 PL030_RTC registers
5-43 PL031_RTC ports
5-44 PL031_RTC registers
5-45 PL041_AACI ports
5-46 PL041_AACI registers
5-47 AudioOut_File ports
5-48 AudioOut_File parameters
5-49 AudioOut_SDL ports
5-50 PL050_KMI ports
5-51 PL050_KMI registers
5-52 PS2Keyboard ports
5-53 PS2Mouse ports
5-54 PL061_GPIO ports
5-55 PL061_GPIO registers
5-56 PL080_DMAC ports
5-57 PL080_DMAC parameters
5-58 PL080_DMAC registers
5-59 PL110_CLCD ports
5-60 PL110_CLCD parameters
5-61 PL110_CLCD registers
5-62 PL111_CLCD ports
5-63 PL111_CLCD parameters
5-64 PL111_CLCD registers
5-65 PL180_MCI ports
5-66 PL180_MCI registers
5-67 MMC ports
5-68 MMC parameters
5-69 MMC registers
5-70 PL192_VIC ports
5-71 PL192_VIC registers
5-72 PL310_L2CC ports
5-73 PL310_L2CC parameters
5-74 PL310_L2CC registers
5-75 PL330_DMAC ports
5-76 PL330_DMAC parameters
5-77 PL330_DMAC registers
5-78 PL340_DMC ports
5-79 PL340_DMC parameters
5-80 PL340_DMC registers
5-81 PL350_SMC ports
5-82 PL350_SMC parameters
5-83 PL350_SMC registers
5-84 PL350_SMC_NAND_FLASH ports
5-85 PL350_SMC_NAND_FLASH parameters
5-86 PL390_GIC ports
5-87 PL390_GIC parameters
5-88 PL 390_GIC registers: distributor interface
5-89 SP804_Timer ports
5-90 SP804_Timer registers
5-91 SP805_Watchdog ports
5-92 SP805_Watchdog parameters
5-93 SP805_Watchdog registers
5-94 SP810_SysCtrl ports
5-95 SP810_SysCtrl parameters
5-96 SP810_SysCtrl registers
5-97 TZIC ports
5-98 TZIC registers
5-99 RemapDecoder ports
5-100 BP135_AXI2APB ports
5-101 BP141_TZMA security control
5-102 BP141_TZMA ports
5-103 BP141_TZMA parameters
5-104 BP147_TZPC ports
5-105 BP147_TZPC registers
5-106 AndGate ports
5-107 OrGate ports
5-108 od to scale conversion
5-109 ICS307 ports
5-110 ICS307 parameters
5-111 ElfLoader ports
5-112 ElfLoader parameters
5-113 FlashLoader ports
5-114 FlashLoader parameters
5-115 IntelStrataFlashJ3 component ports
5-116 IntelStrataFlashJ3 component parameters
5-117 VFS2 ports
5-118 VFS2 parameters
5-119 MessageBox ports
5-120 MessageBox parameters
5-121 MessageBox registers
5-122 RAMDevice ports
5-123 RAMDevice parameters
5-124 SMSC_91C111 ports
5-125 SMSC_91C111 parameters
5-126 SMSC_91C111 bank 0 registers
5-127 SMSC_91C111 bank 1 registers
5-128 SMSC_91C111 bank 2 registers
5-129 SMSC_91C111 bank 3 registers
5-130 HostBridge ports
5-131 HostBridge parameters
5-132 VirtualEthernetCrossover ports
5-133 CCI400 ports
5-134 CCI400 parameters
5-135 DMC_400 ports
5-136 DMC _400 parameters
5-137 GIC_400 ports
5-138 GIC_400 parameters
5-139 MMU_400 ports
5-140 MMU_400 parameters
5-141 TZC_400 ports
5-142 TZC_400 parameters
5-143 MemoryMappedCounterModule ports
5-144 MemoryMappedCounterModule parameters
5-145 v8EmbeddedCrossTrigger_Matrix ports
5-146 v8EmbeddedCrossTrigger_Matrix parameters
5-147 GUIPoll ports
5-148 GUIPoll parameters
6-1 Secure and Non-secure access permissions
6-2 Non-Secure Access IDentity (NSAID) inputs and filters that masters present to the TZC-400
6-3 AEMv8-A Base Platform memory map
6-4 AEMv8-A SPI GIC assignments
6-5 AEMv8-A PPI GIC assignments
6-6 Peripheral clock frequencies in the AEMv8-A Base Platform
6-7 AEMv8-A Base Platform platform parameters
6-8 AEMv8-A Base Platform cluster parameters
6-9 AEMv8-A Base Platform core parameters
6-10 AEMv8-A Base Platform abort parameters
6-11 AEMv8-A Base Platform cache parameters
6-12 AEMv8-A Base Platform cluster memory parameters
6-13 AEMv8-A Base Platform TLB parameters
6-14 AEMv8-A Base Platform debug architecture parameters
6-15 AEMv8-A Base Platform message parameters
6-16 AEMv8-A Base Platform semihosting parameters
6-17 AEMv8-A Base Platform cryptography parameters
6-18 AEMv8-A Base Platform counter module parameters
6-19 AEMv8-A Base Platform timer parameters
6-20 AEMv8-A Base Platform TZC-400 parameters
6-21 AEMv8-A Base Platform trusted watchdog parameters
6-22 AEMv8-A Base Platform CCI-400 parameters
6-23 AEMv8-A Base Platform GICv3 parameters
6-24 AEMv8-A Base Platform power controller parameters
6-25 AEMv8-A Base Platform power controller register summary
6-26 AEMv8-A Base Platform Power Control Processor Off Register bit assignments
6-27 AEMv8-A Base Platform Power Control Processor On Register bit assignments
6-28 AEMv8-A Base Platform Power Control Cluster Off Register bit assignments
6-29 AEMv8-A Base Platform Power Control Wakeup Register bit assignments
6-30 AEMv8-A Base Platform Power Control SYS Status Register bit assignments
6-31 Virtio parameters
6-32 AEMv8-A Base Platform simulator parameters
6-33 AEMv8-A Base Platform UART parameters
6-34 AEMv8-A Base Platform flash block parameters
6-35 AEMv8-A Base Platform flashloader parameters
6-36 AEMv8-A Base Platform networking parameters
6-37 AEMv8-A Base Platform MMC device parameters
6-38 AEMv8-A Base Platform simulator visualization parameters
6-39 AEMv8-A Base Platform other component parameters
7-1 Cortex-A series platform model memory map
7-2 CS2 region peripheral memory map for secure_memory option
7-3 CS2 region peripheral memory map
7-4 CS3 region peripheral memory map
7-5 Memory map
7-6 Peripheral memory map
7-7 VE model instantiation parameters
7-8 VE model secure memory parameters
7-9 Default positions of VE system model switch
7-10 STDIO redirection
7-11 VEVisualisation ports
7-12 VEVisualisation parameters
7-13 VE_SysRegs ports
7-14 VE_SysRegs parameters
7-15 VE_SysRegs registers
8-1 Memory map and interrupts for standard peripherals
8-2 EB model instantiation parameters
8-3 Default positions for EB system model switch S6
8-4 STDIO redirection
8-5 EB System Model switch S8 settings
8-6 EBVisualisation ports
8-7 EBVisualisation parameters
8-8 EB_SysRegs ports
8-9 EB_SysRegs parameters
8-10 EB_SysRegs registers
8-11 EBCortexA9_SysRegs ports
8-12 EBCortexA9_SysRegs registers
8-13 TSC2200 ports
8-14 TSC2200 parameters
9-1 Overview of MPS memory map
9-2 MPS processor system registers
9-3 MPS DUT system registers
9-4 MPS LCD registers
9-5 Memory configuration register
9-6 User switches
9-7 Seven-segment register
9-8 MPSVisualisation interactive controls
9-9 MPSVisualisation ports
9-10 MPSVisualisation parameters
9-11 MPS_CharacterLCD ports
9-12 MPS_CharacterLCD registers
9-13 MPS_DUTSysReg ports
9-14 MPS_DUTSysReg parameters
9-15 MPS_DUTSysReg registers

Release Information

Document History
Issue Date Confidentiality Change
A 28 February 2008 Confidential New document, based on previous documentation.
B 30 June 2008 Confidential Release for v4.0.
C 31 August 2008 Confidential Update for v4.0 SP1.
D 31 December 2008 Confidential Update for v4.1.
E 31 March 2009 Confidential Update for v4.2.
F 31 May 2009 Confidential Release for v5.0.
G 30 September 2009 Confidential Update for v5.1.
H 28 February 2010 Confidential Update for v5.2.
I 31 October 2010 Non-Confidential Release for v6.0.
J 31 May 2011 Non-Confidential Update for v6.1.
K 31 July 2011 Confidential Update for v6.2.
L 30 November 2011 Non-Confidential Release for v7.0.
M 31 May 2012 Non-Confidential Update for v7.1.
N 31 December 2012 Non-Confidential Release for v8.0.
O 31 May 2013 Non-Confidential Update for v8.1.
P 31 August 2013 Non-Confidential Update for v8.2.
Q 30 November 2013 Non-Confidential Update for v8.3.
R 31 May 2014 Confidential Update for v8.4.

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