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| Home > Introduction > About the baseboard Real-Time System Models | |||
The Real-Time System Models for the EB Reference System model the following components:
Processor core tile options:
Cortex™-A9
Cortex-A8
Cortex-R4
ARM1176JZF-S™
ARM1136JF-S™
ARM926EJ-S™.
Emulation Baseboard model with:
64MB Flash memory
256MB RAM
ethernet interface
UART interface
visualization for CLCD display, keyboard and mouse
debug DIP switches and LEDs
interrupt controllers
Real-Time Clock (RTC)
time of year clock
programmable clock generators
Synchronous Serial Port Interface (SSPI)
DMA controller configuration registers
Static Memory Controller (SMC).
The EB RTSM also includes virtual components:
a virtual file system, implemented through the VFS2 component
touch screen controller
four telnet terminals.
The Real-Time System Models for the EB Reference System are hierarchical models that consist of:
the top-level view of the model
the Emulation Baseboard model
the Core Tile model that is used by the system model.
The Emulation Baseboard RTSMs provide a functionally-accurate model for software execution. However, the model sacrifices timing accuracy in favor of fast simulation speeds. Key deviations from actual hardware are:
timing is approximate
buses are simplified
caches for architecture v5 and v6 processors, and write buffers, are not implemented.
Further details on differences between the EB hardware and the RTSMs in Differences between the EB hardware and the system model.
The EB RTSMs are provided as example platform implementations and are not intended to be accurate representations of a specific EB hardware revision. The RTSMs support selected peripherals as described in this book. The supplied RTSMs are sufficiently complete and accurate to boot the same operating system images as for EB hardware.
Many components can be configured at instantiation time. See Model configuration parameters.