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Table 3.13 lists the Cortex-A8 core tile RTSM parameters that you can change when you start the model. All listed parameters are instantiation-time parameters. This core tile RTSM is based on r2p1 of the Cortex-A8 processor.
The syntax to use in a configuration file is:
coretile.core. parameter=value
Table 3.13. ARMCortexA8CT RTSM parameters
| Parameter | Description | Type | Values | Default |
|---|---|---|---|---|
| CFGEND0 | Initialize to BE8 endianness. | boolean | true/false | false |
| CFGNMFI | Enable non-maskable interrupts on startup. | boolean | true/false | false |
| CFGTE | Initialize to take exceptions in Thumb state. Model starts in Thumb state. | boolean | true/false | false |
| CP15SDISABLE | Initialize to disable access to some CP15 registers. | boolean | true/false | false |
| UBITINIT | Initialize to ARMv6 unaligned behavior. | boolean | true/false | false |
| VINITHI | Initialize with high vectors enabled. | boolean | true/false | false |
| l1_dcache-state_modelled[1] | Include level 1 data cache state model. | boolean | true/false | false |
| l1_icache-state_modelled[1] | Include level 1 instruction cache state model. | boolean | true/false | false |
| l2_cache-state_modelled[1] | Include unified level 2 cache state model. | boolean | true/false | false |
| implements_vfp | Set whether CT model has been built with VFP support. | boolean | true/false | true |
| semihosting-cmd_line | Command line available to semihosting SVC calls. | string | no limit except memory | [empty string] |
| semihosting-debug[2] | Enable debug output of semihosting SVC calls. | boolean | true/false | false |
| semihosting-enable | Enable semihosting SVC traps. | boolean | true/false | true |
| semihosting-ARM_SVC | ARM SVC number for semihosting. | integer | 24 bit integer | 0x123456 |
| semihosting-Thumb_SVC | Thumb SVC number for semihosting. | integer | 8 bit integer | 0xAB |
| semihosting-heap_base | Virtual address of heap base. | integer | 0x00000000 - 0xFFFFFFFF | 0x0 |
| semihosting-heap_limit | Virtual address of top of heap. | integer | 0x00000000 - 0xFFFFFFFF | 0x0F000000 |
| semihosting-stack_base | Virtual address of base of descending stack. | integer | 0x00000000 - 0xFFFFFFFF | 0x10000000 |
| semihosting-stack_limit | Virtual address of stack limit. | integer | 0x00000000 - 0xFFFFFFFF | 0x0F0000000 |
| siliconID[3] | Value read by system coprocessor siliconID register. | integer | 32 bit integer | 0x41000000 |
| vfp-enable_at_reset | Enable coprocessor access and VFP at reset.[4] | boolean | true/false | false |
[1] These three parameters allow you to define the cache state in your model. The default setting is for no caches. Any combination of true/false settings for the cache state parameters is valid. For example, if all three parameters are set to true, your model has L1 and L2 caches. [2] Currently ignored. [3] This parameter is not intended to be modified by the user. [4] This is model specific behavior with no hardware equivalent. | ||||
The Cortex-A8 core tile RTSM also includes a GIC but this cannot be configured at instantiation time.
| Copyright © 2008 ARM Limited. All rights reserved. | ARM DUI0424B |
| Non-Confidential | Unrestricted Access |
| PDF version | |
| Home > Programmer’s Reference > Model configuration parameters > ARMCortexA8CT RTSM parameters |