RealView Development Suite Real-Time System Models User Guide: 3.2.7. RTSM_EB

3.2.7. RTSM_EB_Cortex-A8 core tile parameters

Table 3.11 lists the Cortex-A8 core tile RTSM parameters that you can change when you start the model. All listed parameters are instantiation-time parameters. This core tile RTSM is based on r2p1 of the Cortex-A8 processor.

The syntax to use in a configuration file is:

coretile.core.parameter=value

Table 3.11. RTSM_EB_Cortex-A8 core tile parameters

Parameter	Description	Type	Values	Default
`semihosting-cmd_line`	Command line available to semihosting SVC calls.	string	no limit except memory	[empty string]
`semihosting-debug`^[a]	Enable debug output of semihosting SVC calls.	boolean	`true` or `false`	`false`
`semihosting-enable`	Enable semihosting SVC traps.	boolean	`true` or `false`	`true`
`semihosting-ARM_SVC`	ARM SVC number for semihosting.	integer	24 bit integer	`0x123456`
`semihosting-Thumb_SVC`	Thumb SVC number for semihosting.	integer	8 bit integer	`0xAB`
`semihosting-heap_base`	Virtual address of heap base.	integer	`0x00000000 - 0xFFFFFFFF`	`0x0`
`semihosting-heap_limit`	Virtual address of top of heap.	integer	`0x00000000 - 0xFFFFFFFF`	`0x0F000000`
`semihosting-stack_base`	Virtual address of base of descending stack.	integer	`0x00000000 - 0xFFFFFFFF`	`0x10000000`
`semihosting-stack_limit`	Virtual address of stack limit.	integer	`0x00000000 - 0xFFFFFFFF`	`0x0F0000000`
^[a]Currently ignored.

The Cortex-A8 core tile RTSM also includes a GIC but this cannot be configured at instantiation time.

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