3.10.2. Restrictions on the processor models

For detailed information concerning what features are not fully implemented in the processor models included with the EB RTSMs, see the Fast Models Reference Manual. The following general restrictions apply to the Real-Time System Model implementations of ARM processors:

RTSM_EB_Cortex-A8 CoreTile

The following additional restrictions apply to the Real-Time System Model implementation of the Cortex-A8 processor:

  • Two 4GB address spaces are seen by the model core, one as seen from secure mode and one as seen from normal mode. The address spaces contain zero-wait state memory and peripherals, but a lot of the space is unmapped.

  • The PLE model is purely register-based and has no implemented behavior.

  • VFP and NEON instruction set execution on the model is not high performance.

  • Unaligned accesses with the MMU disabled do not cause data aborts.

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