3.1. EB model memory map

Table 3.1 lists the locations and interrupts for memory, peripherals, and controllers used in the EB Real-Time System Models. See the Emulation Baseboard User Guide for more details on the controllers and peripherals.

Table 3.1. Memory map and interrupts for standard peripherals

PeripheralModeledAddress rangeBusSizeGIC Int[a]DCCIInt[b]

Dynamic memory

Yes0x00000000-0x0FFFFFFFAHB256MB--
System registers (see Status and system control registers)Yes0x10000000-0x10000FFFAPB4KB--
SP810 System ControllerYes0x10001000-0x10001FFFAPB4KB--
Two-Wire Serial Bus InterfaceNo0x10002000-0x10002FFFAPB4KB--
Reserved-0x10003000-0x10003FFFAPB4KB--
PL041 Advanced Audio CODEC Interface (AACI)Partial[c]0x10004000-0x10004FFFAPB4KB5151
PL180 MultiMedia Card Interface (MCI)Partial[d]0x10005000-0x10005FFFAPB4KB49, 5049, 50
Keyboard/Mouse Interface 0 Yes0x10006000-0x10006FFFAPB4KB527
Keyboard/Mouse Interface 1Yes0x10007000-0x10007FFFAPB4KB538
Character LCD InterfaceNo0x10008000-0x10008FFFAPB4KB5555
UART 0 InterfaceYes

0x10009000-0x10009FFF

APB4KB444
UART 1 InterfaceYes

0x1000A000-0x1000AFFF

APB4KB455
UART 2 Interface Yes

0x1000B000-0x1000BFFF

APB4KB4646
UART 3 Interface Yes

0x1000C000-0x1000CFFF

APB4KB4747
Synchronous Serial Port InterfaceYes

0x1000D000-0x1000DFFF

APB4KB4343
Smart Card InterfaceNo 0x1000E000-0x1000EFFFAPB4KB6262
Reserved-0x1000F000-0x1000FFFFAPB4KB--

SP805 Watchdog Interface

Yes

0x10010000-0x10010FFF

APB4KB3232

SP804 Timer modules 0 and 1 interface

(Timer 1 starts at 0x10011020)

Yes

0x10011000-0x10011FFF

APB4KB361

SP804 Timer modules 2 and 3 interface

(Timer 3 starts at 0x10020020)

Yes

0x10012000-0x10012FFF

APB4KB372

PL061 GPIO Interface 0

Yes

0x10013000-0x10013FFF

APB4KB3838

PL061 GPIO Interface 1

Yes

0x10014000-0x10014FFF

APB4KB3939

PL061 GPIO Interface 2 (miscellaneous onboard I/O)

Yes

0x10015000-0x10015FFF

APB4KB4040
Reserved-

0x10016000-0x10016FFF

APB4KB--

PL030 Real-Time Clock Interface

Yes

0x10017000-0x10017FFF

APB4KB--
Dynamic Memory Controller configurationPartial[e]

0x10018000-0x10018FFF

APB4KB--

PCI controller configuration registers

No0x10019000-0x10019FFFAHB4KB--
Reserved -0x1001A000-0x1001FFFFAPB24KB --

PL111 Color LCD Controller

Yes0x10020000-0x1002FFFFAHB64KB5555

DMA Controller configuration registers

Yes 0x10030000-0x1003FFFFAHB64KB--

Generic Interrupt Controller 1

CPU interface

Yesb0x10040000-0x10040FFFAHB4KB--

Generic Interrupt Controller 1

Distributor interface

Yes0x10041000-0x10041FFFAHB4KB--

Generic Interrupt Controller 2

CPU interface (nFIQ for tile 1)

No[f]0x10050000-0x10050FFFAHB4KB--

Generic Interrupt Controller 2

Distributor interface

Yes0x10051000-0x10051FFFAHB4KB--

Generic Interrupt Controller 3

CPU interface (nIRQ for tile 2)

No[f]0x10060000-0x10060FFFAHB4KB--

Generic Interrupt Controller 3

Distributor interface

No0x10061000-0x10061FFFAHB4KB--

Generic Interrupt Controller 4

CPU interface (nFIQ for tile 2)

No[f]0x10070000-0x10070FFFAHB4KB--

Generic Interrupt Controller 4

Distributor interface

No0x10071000-0x10071FFFAHB4KB--

PL350 Static Memory Controller configuration[g]

Yes0x10080000-0x1008FFFFAHB64KB--
Reserved -

0x10090000-0x100EFFFF

AHB448MB--
Debug Access Port (DAP) ROM table. Some debuggers read information on the target processor and the debug chain from the DAP table. No0x100F0000-0x100FFFFFAHB64KB--
Reserved -

0x10100000-0x1FFFFFFF

-255MB--
Reserved -

0x20000000-0x3FFFFFFF

-512MB--
NOR FlashYes[h]

0x40000000-0x43FFFFFF

AXI64MB--
Disk on ChipNo

0x44000000-0x47FFFFFF

AXI64MB4141
SRAMYes0x48000000-0x4BFFFFFFAXI64MB--
Configuration flashNo0x4C000000-0x4DFFFFFFAXI32MB--
EthernetYes[i]0x4E000000-0x4EFFFFFFAXI16MB6060
USBNo0x4F000000-0x4FFFFFFFAXI16MB--
PISMO expansion memoryNo0x50000000-0x5FFFFFFFAXI256MB5858

PCI interface bus windows

No0x60000000-0x6FFFFFFFAXI256MB--
Dynamic memory (mirror)Yes0x70000000-0x7FFFFFFFAXI256MB--
Memory tile (Second CoreTile)Yes0x70000000-0x7FFFFFFFAXI0 to 1GB--

[a] The Interrupt signal column lists the value to use to program your interrupt controller. The values shown are after mapping the SPI number by adding 32. The interrupt numbers from the peripherals are modified by adding 32 to form the interrupt number seen by the GIC. GIC interrupts 0-31 are for internal use.

[b] The numbers in this column are the interrupt numbers used by the DCCI system.

[c] See Sound.

[d] The implementation of the PL180 is limited, so not all features are present.

[f] The EB RTSM GICs are not the same as those implemented on the EB hardware as the register map is different. See Generic Interrupt Controller.

[g] Although the EB hardware uses the PL093 static memory controller, the model implements PL350. These are functionally equivalent.

[h] This peripheral is implemented in the IntelStrataFlashJ3 component in the EB RTSM.

[i] This peripheral is implemented in the SC91C111 component in the EB RTSM.


Note

The EB RTSM implementation of memory does not require programming the memory controller with the correct values.

This means you must ensure that the memory controller is set up properly if you run an application on actual hardware. If this is not done, applications that run on an RTSM might fail on actual hardware.

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