3.9. RTSM_EB_Cortex-A8 CoreTile parameters

Table 3.11 lists the Cortex-A8 CoreTile RTSM parameters that you can change when you start the model. All listed parameters are instantiation-time parameters. This CoreTile RTSM is based on r2p1 of the Cortex-A8 processor.

The syntax to use in a configuration file is:

coretile.core.parameter=value

Table 3.11. RTSM_EB_Cortex-A8 CoreTile parameters

ParameterDescriptionTypeValuesDefault
semihosting-cmd_lineCommand line available to semihosting SVC calls.stringno limit except memory[empty string]
semihosting-debug[a]Enable debug output of semihosting SVC calls.booleantrue or falsefalse
semihosting-enableEnable semihosting SVC traps.booleantrue or falsetrue
semihosting-ARM_SVCARM SVC number for semihosting.integer24 bit integer0x123456
semihosting-Thumb_SVCThumb SVC number for semihosting.integer8 bit integer0xAB
semihosting-heap_baseVirtual address of heap base.integer0x00000000 - 0xFFFFFFFF0x0
semihosting-heap_limitVirtual address of top of heap.integer0x00000000 - 0xFFFFFFFF0x0F000000
semihosting-stack_baseVirtual address of base of descending stack.integer0x00000000 - 0xFFFFFFFF0x10000000
semihosting-stack_limitVirtual address of stack limit.integer0x00000000 - 0xFFFFFFFF0x0F0000000

[a] Ignored.


The Cortex-A8 CoreTile RTSM also includes a GIC but this cannot be configured at instantiation time.

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