2.3.1. Using the EB CLCD window

Figure 2.1 shows the EB RTSM CLCD in its default state, immediately after being started.

Figure 2.1. CLCD window at startup

CLCD window at startup

The top section of the CLCD window displays the following status information:

USERSW

Eight white boxes show the state of the EB User DIP switches:

These represent switch S6 on the EB hardware, USERSW[8:1], which is mapped to bits [7:0] of the SYS_SW register at address 0x10000004.

The switches are in the off position by default. Click in the area above or below a white box to change its state. See Switch S6.

BOOTSW

Eight white boxes showing the state of the EB Boot DIP switches.

These represent switch S8 on the EB hardware, BOOTSEL[8:1], which is mapped to bits [15:8] of the SYS_SW register at address 0x100000004.

The switches are in the off position by default. See Switch S8.

Note

ARM recommends you configure the Boot DIP switches using the boot_switch model parameter rather than by using the CLCD interface.

Changing Boot DIP switch positions while the model is running can result in unpredictable behavior.

S6LED

Eight colored boxes indicate the state of the EB User LEDs.

These represent LEDs D[21:14] on the EB hardware, which are mapped to bits [7:0] of the SYS_LED register at address 0x10000008. The boxes correspond to the red/yellow/green LEDs on the EB hardware.

Total Instr

A counter showing the total number of instructions executed.

Because the RTSM models provide a programmer’s view of the system, the CLCD displays total instructions rather than total core cycles. Timing might differ substantially from the hardware because:

  • the bus fabric is simplified

  • memory latencies are minimized

  • programmer’s view core and peripheral models are used.

In general, the timing of operations within a model is not accurate.

Total Time

A counter showing the total elapsed time, in seconds.

This is wall clock time, not simulated time.

Rate Limit

A feature that prevents the simulation from running faster than wall clock time.

Because the system model is highly optimized, your code might run faster than it would on real hardware. This might cause timing issues.

Rate Limit is enabled by default. Simulation time is restricted so that it more closely matches real time. See Timing considerations.

Click on the square button to disable or enable Rate Limit. The text changes from ON to OFF and the colored box becomes darker when Rate Limit is disabled. Figure 2.2 shows the CLCD with Rate Limit disabled.

Note

You can control whether Rate Limit is enabled by using the rate_limit-enable parameter when instantiating the model. See Visualization parametersVisualization parameters.

If you click on the Total Instr or Total Time items in the CLCD, the display changes to show Inst/sec (instructions per second) and Perf Index (performance index) as shown in Figure 2.2. You can click on the items again to toggle between the original and alternative displays.

Figure 2.2. CLCD window with Rate Limit off

CLCD window with Rate Limit off

Instr/sec

Shows the number of instructions executed per second of wall clock time.

Perf Index

The ratio of real time to simulation time. The larger the ratio, the faster the simulation runs. If you enable the Rate Limit feature, the Perf Index approaches unity.

You can reset the simulation counters by resetting the model.

If the CLCD window has focus:

Note

The simulator only sends relative mouse motion events to the model. As a result, the host mouse pointer does not necessarily align with the target OS mouse pointer.

You can hide the host mouse pointer by pressing the Left Ctrl+Left Alt keys. Press the keys again to redisplay the host mouse pointer. Only the Left Ctrl key is operational. The Right Ctrl key on the right of the keyboard does not have the same effect.

If you prefer to use a different key, use the trap_key configuration option. See the CADI parameter documentation in the Fast Models Reference Manual.

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