3.1 EB model memory map

This section describes the locations and interrupts of the memory, peripherals, and controllers that the EB Fixed Virtual Platforms use.

The EB FVP implementation of memory does not require you to program the memory controller with the correct values. To avoid application failure on hardware, be sure to set up the memory controller properly.

Table 3-1 Memory map and interrupts for standard peripherals

Peripheral Modeled Address range Bus Size GIC Inta DCCI Intb
Dynamic memory Yes 0x000000000x0FFFFFFF AHB 256MB - -
System registers Yes 0x100000000x10000FFF APB 4KB - -
SP810 System Controller Yes 0x100010000x10001FFF APB 4KB - -
Two-Wire Serial Bus Interface No 0x100020000x10002FFF APB 4KB - -
Reserved - 0x100030000x10003FFF APB 4KB - -
PL041 Advanced Audio CODEC Interface (AACI) Partial 0x100040000x10004FFF APB 4KB 51 51
PL180 MultiMedia Card Interface (MCI) Partialc 0x100050000x10005FFF APB 4KB 49, 50 49, 50
Keyboard/Mouse Interface 0 Yes 0x100060000x10006FFF APB 4KB 52 7
Keyboard/Mouse Interface 1 Yes 0x100070000x10007FFF APB 4KB 53 8
Character LCD Interface No 0x100080000x10008FFF APB 4KB 55 55
UART 0 Interface Yes
APB 4KB 44 4
UART 1 Interface Yes
APB 4KB 45 5
UART 2 Interface Yes
APB 4KB 46 46
UART 3 Interface Yes
APB 4KB 47 47
Synchronous Serial Port Interface Yes
APB 4KB 43 43
Smart Card Interface No 0x1000E0000x1000EFFF APB 4KB 62 62
Reserved - 0x1000F0000x1000FFFF APB 4KB - -
SP805 Watchdog Interface Yes
APB 4KB 32 32
SP804 Timer modules 0 and 1 interface (Timer 1 starts at 0x10011020) Yes
APB 4KB 36 1
SP804 Timer modules 2 and 3 interface (Timer 3 starts at 0x10012020) Yes
APB 4KB 37 2
PL061 GPIO Interface 0 Yes
APB 4KB 38 38
PL061 GPIO Interface 1 Yes
APB 4KB 39 39
PL061 GPIO Interface 2 (miscellaneous onboard I/O) Yes
APB 4KB 40 40
Reserved -
APB 4KB - -
PL030 Real-Time Clock Interface Yes
APB 4KB - -
Dynamic Memory Controller configuration Partial
APB 4KB - -
PCI controller configuration registers No 0x100190000x10019FFF AHB 4KB - -
Reserved - 0x1001A0000x1001FFFF APB 24KB - -
PL111 Color LCD Controller
Yes 0x100200000x1002FFFF AHB 64KB 55 55
DMA Controller configuration registers Yes 0x100300000x1003FFFF AHB 64KB - -
Generic Interrupt Controller 1 (CPU interface) Yesd 0x100400000x10040FFF AHB 4KB - -
Generic Interrupt Controller 1 (Distributor interface) Yes 0x100410000x10041FFF AHB 4KB - -
Generic Interrupt Controller 2 [CPU interface (nFIQ for tile 1)] Nod 0x100500000x10050FFF AHB 4KB - -
Generic Interrupt Controller 2 (Distributor interface) Yes 0x100510000x10051FFF AHB 4KB - -
Generic Interrupt Controller 3 [CPU interface (nIRQ for tile 2)] Nod 0x100600000x10060FFF AHB 4KB - -
Generic Interrupt Controller 3 (Distributor interface) No 0x100610000x10061FFF AHB 4KB - -
Generic Interrupt Controller 4 [CPU interface (nFIQ for tile 2)] Nod 0x100700000x10070FFF AHB 4KB - -
Generic Interrupt Controller 4 (Distributor interface) No 0x100710000x10071FFF AHB 4KB - -
PL350 Static Memory Controller configuratione Yes 0x100800000x1008FFFF AHB 64KB - -
Reserved -
AHB 448MB - -
Debug Access Port (DAP) ROM tablef No 0x100F00000x100FFFFF AHB 64KB - -
Reserved -
- 255MB - -
Reserved -
- 512MB - -
NOR Flash Yesg
AXI 64MB - -
Disk on Chip No
AXI 64MB 41 41
SRAM Yes 0x480000000x4BFFFFFF AXI 64MB - -
Configuration flash No 0x4C0000000x4DFFFFFF AXI 32MB - -
Ethernet Yesh 0x4E0000000x4EFFFFFF AXI 16MB 60 60
USB No 0x4F0000000x4FFFFFFF AXI 16MB - -
PISMO expansion memory No 0x500000000x5FFFFFFF AXI 256MB 58 58
PCI interface bus windows No 0x600000000x6FFFFFFF AXI 256MB - -
Dynamic memory (mirror) Yes 0x700000000x7FFFFFFF AXI 256MB - -
Memory tile (Second CoreTile) Yes 0x700000000x7FFFFFFF AXI 0GB to 1GB - -
Related reference
3.3.2 Features partially implemented in the baseboard model
3.3.6 Status and system control registers
3.3.7 Generic Interrupt Controller
Related information
Controllers and peripherals, Emulation Baseboard User Guide (Lead Free)
a Add 32 to interrupt numbers from the peripherals (SPIs) to form the interrupt numbers that the GIC sees. GIC interrupts 0-31 are for internal use.
b Interrupt numbers that the DCCI system uses.
c The implementation of the PL180 is limited, so not all features are present.
d The EB FVP GICs differ from the EB hardware GICs because the register map is different.
e Although the EB hardware uses the PL093 static memory controller, the model implements PL350. These components are functionally equivalent.
f Some debuggers read information on the target processor and the debug chain from the DAP table.
g In EB FVPs, the IntelStrataFlashJ3 component implements this peripheral.
h In EB FVPs, the SC91C111 component implements this peripheral.
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