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| Home > Programmer’s Reference > Interrupt controllers in the ARM1176JZF-S development chip > Development chip TrustZone Interrupt Controller |
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This section describes the registers in the ARM1176JZF-S development chip TrustZone Interrupt controller.
Table 4.50. TZIC implementation in development chip
| Property | Value |
|---|---|
| Location | ARM1176JZF-S development chip |
| Memory base addresses |
|
| Interrupt inputs | See Table 4.71. |
| Interrupt output | TZIC output is connected to the development chip CPU nFIQ input. |
| Release version | Custom implementation of the ARM SP890 TZIC. |
| Reference documentation | This section. |
Table 4.51 summarizes the registers in base offset order.
Table 4.51. TZIC register summary
| Name | Offset | Type | Reset value | Description |
|---|---|---|---|---|
| TZICFIQStatus | 0x000 | RO | 0x00000000 | See FIQ status register |
| TZICRawIntr | 0x004 | RO | - | See Raw interrupt status register |
| TZICIntSelect | 0x008 | R/W | 0x00000000 | See Interrupt select register |
| TZICFIQEnable | 0x00C | R/W | 0x00000000 | See FIQ enable register |
| TZICFIQENClear | 0x010 | WO | - | See FIQ enable clear register |
| TZICFIQBypass | 0x014 | R/W | 0x00000000 | See FIQ bypass register |
| TZICProtection | 0x018 | R/W | 0x00000000 | See Protection register |
| TZICLock | 0x01C | WO | - | See Lock enable register |
| TZICLockStatus | 0x020 | RO | 0x00000001 | See Lock status register |
| Test registers | 0x300-0x310 | - | - | Reserved. Do not use. |
| TZICPeriphID0 | 0xFE0 | RO | 0x00000090 | See Peripheral identification registers TZICPeriphlDx |
| TZICPeriphID1 | 0xFE4 | RO | 0x00000018 | |
| TZICPeriphID2 | 0xFE8 | RO | 0x00000004 | |
| TZICPeriphID3 | 0xFEC | RO | 0x00000000 | |
| TZICPCellID0 | 0xFF0 | RO | 0x0000000D | See TZICPCellID0 Register |
| TZICPCellID1 | 0xFF4 | RO | 0x000000F0 | |
| TZICPCellID2 | 0xFF8 | RO | 0x00000005 | |
| TZICPCellID3 | 0xFFC | RO | 0x000000B1 |
The read-only TZICFIQStatus Register has a reset value of 0x00000000.
It provides the status of the interrupts after FIQ masking. Table 4.52 lists the register
bit assignments.
Table 4.52. TZICFIQStatus Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:0] | FIQStatus | Shows the status of the interrupts after masking by the TZICFIQIntEnable and TZICFIQIntEnClear Registers. A HIGH bit indicates that the interrupt is active, and generates an nFIQ interrupt to the processor. |
The read-only TZICRawIntr Register provides the status of the source interrupts, and software interrupts, to the interrupt controller. Table 4.53 lists the register bit assignments.
Table 4.53. TZICRawIntr Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:0] | RawIntr | Shows the status of the interrupts before masking by the TZICFIQIntEnable and TZICFIQIntEnClear Registers. A HIGH bit indicates that the interrupt is active before masking. |
The read-write TZICIntSelect Register has a reset value of 0x00000000.
It selects whether you can use the corresponding input source to
generate a FIQ interrupt or whether it passes through to TZICIRQOUT. Table 4.54 lists the register bit assignments.
Table 4.54. TZICIntSelect Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:0] | IntSelect | Selects whether the interrupt source generates an FIQ interrupt or passes straight through to TZICIRQOUT. 0 = interrupt passes through to TZICIRQOUT 1 = interrupt is available for FIQ generation. |
The read/write TZICFIQEnable Register has a reset value of 0x00000000.
It enables the corresponding FIQ-selected input source. This interrupt
source can then generate an FIQ interrupt. Table 4.55 lists the register bit assignments.
Table 4.55. TZICFIQEnable Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:0] | FIQEnable | Enables the FIQ-selected interrupt lines, allowing the interrupts to reach the processor. Read: 0 = interrupt disabled 1 = interrupt enabled. You can only enable the interrupt using this register. You must use the TZICFIQEnClear Register to disable the interrupt enable. Write: 0 = no effect 1 = interrupt enabled. Resetting disables all interrupts. There is 1 bit of the register for each interrupt source. |
The write-only TZICFIQEnClear Register clears bits in the TZICFIQEnable Register. See FIQ enable register. Table 4.56 lists the register bit assignments.
Table 4.56. TZICFIQEnClear Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:0] | FIQEnClear | Clears bits in the TZICFIQEnable Register. Writing a HIGH clears the corresponding bit in the TZICFIQEnable Register. Writing a LOW has no effect. |
The read/write TZICFIQBypass Register has a reset value of 0x00000000.
It enables nNSFIQIN to be routed
directly to nFIQ. By doing this, it bypasses all internal TZIC logic.
Figure 4.14 shows the register bit assignments.
Table 4.57 lists the register bit assignments.
Table 4.57. TZICFIQBypass Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:1] | - | Read undefined. Write as zero. |
| [0] | FIQBypass | Enables nNSFIQIN to route directly to nFIQ. 0=No Bypass 1=Bypass. |
The read/write TZICProtection Register has a reset value of 0x00000000.
It enables or disables protected register access, stopping register
accesses when the processor is in user-mode.
Figure 4.15 shows the register bit assignments.
Table 4.58 lists the register bit assignments.
Table 4.58. TZICProtection Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:1] | - | Read undefined. Write as zero. |
| [0] | Protection | Enables or disables protected register access: 0 = protection mode disabled 1 = protection mode enabled. When enabled, you can only make privileged mode accesses (reads and writes) to the TZIC. You can only access this register in privileged mode, even when protection mode is disabled. |
The write-only TZICLock Register enables or disables all other register write access. You must write the access code to this register before you can modify any other register. To disable access, you must write any other value to the register. The register protects the TZIC from spurious writes. The Lock bit in the TZICLockStatus Register indicates the status of the lock. See FIQ status register. Table 4.59 lists the register bit assignments.
Table 4.59. TZICLock Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:0] | Lock | To enable access to the other registers in
the TZIC, you must write the correct access code of 0x0ACCE550 to
this register. To disable access to the other TZIC registers, you
must write any other value than 0x0ACCE550 to
this register. |
The read-only TZICLockStatus Register provides the lock status of the TZIC registers.
Figure 4.16 shows the register bit assignments.
Table 4.60 lists the register bit assignments.
Table 4.60. TZICLockStatus Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:1] | - | Read undefined. |
| [0] | Locked | Shows the locked status of the TZIC: 0 = Access to the TZIC is not locked 1 = Access to the TZIC is locked (reset). You can unlock the access using the TZICLock Register. |
The read-only TZICPeriphlD0-3 Registers are four 8-bit registers
that span address locations 0xFE0 to 0xFEC.
You can treat the registers conceptually as a single 32-bit register.
Figure 4.17 shows the register bit assignments of the TZICPeriphlD0-3 registers.
Table 4.61 lists the peripheral identification registers bit assignments.
Table 4.61. TZICPeriphlD0-3 Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:24] | Configuration | Configuration option of the peripheral. The configuration value is 0. |
| [23:20] | Revision number | Revision number of the peripheral. The revision number starts from 0, and the value is revision independent. |
| [19:12] | Designer | Identification of the designer. ARM Limited
is 0x41 (ASCII A). |
| [11:0] | Part number | Identification of the peripheral. Use the three-digit
product code 0x890 for TZIC. |
The read-only TZICPeriphID0 Register is hard-coded and the register fields register determine the reset value.
Figure 4.18 shows the register bit assignments.
Table 4.62 lists the register bit assignments.
Table 4.62. TZICPeriphID0 Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Read undefined |
| [7:0] | Partnumber0 | These bits read back as 0x90 |
See also:
The read-only TZICPeriphID1 Register is hard-coded and the fields within the register determine the reset value.
Figure 4.19 shows the register bit assignments.
Table 4.63 lists the register bit assignments.
Table 4.63. TZICPeriphID1 Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Read undefined |
| [7:4] | Designer0 | These bits read back as 0x1 |
| [3:0] | Partnumber1 | These bits read back as 0x8 |
The read-only TZICPeriphID2 Register is hard-coded and the fields within the register determine the reset value.
Figure 4.20 shows the register bit assignments.
Table 4.64 lists the register bit assignments.
Table 4.64. TZICPeriphID2 Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Read undefined |
| [7:4] | Revision | These bits read back as the revision number and can be between 0 and 15 |
| [3:0] | Designer1 | These bits read back as 0x4 |
The read-only TZICPeriphID3 Register is hard-coded and the fields within the register determine the reset value.
Figure 4.21 shows the register bit assignments.
Table 4.65 lists the register bit assignments.
Table 4.65. TZICPeriphID3 Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Read undefined |
| [7:0] | Configuration | These bits read back as 0x00 |
The read-only TZICPCelllD0-3 registers are four 8-bit registers
that span address locations 0xFF0 to 0xFFC.
You can treat the registers conceptually as a single 32-bit register.
This register acts as a standard cross-peripheral identification
system. Figure 4.22 shows
the register bit assignments.
The read-only TZICPCellID0 Register is hard-coded and the fields within the register determine the reset value. Table 4.66 lists the register bit assignments.
Table 4.66. TZICPCellID0 Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Read undefined |
| [7:0] | TZICPCellID0 | These bits read back as 0x0D |
See also:
The read-only TZICPCellID1 Register is hard-coded and the fields within the register determine the reset value. Table 4.67 lists the register bit assignments.
Table 4.67. TZICPCellID1 Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Read undefined |
| [7:0] | TZICPCellID1 | These bits read back as 0xF0 |
The read-only TZICPCellID2 Register is hard-coded and the fields within the register determine the reset value. Table 4.68 lists the register bit assignments.
Table 4.68. TZICPCellID2 Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Read undefined |
| [7:0] | TZICPCellID2 | These bits read back as 0x05 |
The read-only TZICPCellID3 Register is hard-coded and the fields within the register determine the reset value. Table 4.69 lists the register bit assignments.
Table 4.69. TZICPCellID3 Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:8] | - | Read undefined |
| [7:0] | TZICPCellID3 | These bits read back as 0xB1 |
| Copyright © 2007-2011 ARM Limited. All rights reserved. | ARM DUI 0425F |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Reference > Interrupt controllers in the ARM1176JZF-S development chip > Development chip TrustZone Interrupt Controller |