RealView Platform Baseboard for ARM1176JZF-S User Guide: 4.9.7. Configuration registers SYS_CFGDATAx

RealView Platform Baseboard for ARM1176JZF-S User Guide

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4.9.7. Configuration registers SYS_CFGDATAx

The read/write registers SYS_CFGDATA1 (at 0x10000028) and SYS_CFGDATA2 (at 0x1000002C) contain configuration data. See Table 4.37 and Table 4.38 for the function associated with the register bits.

Note

The values of SYS_GFGDATA1 and SYS_CFGDATA2 are loaded at reset (DEVCHIPRECONFIG) into the SoC Config registers of the processor.

In a production ASIC, the configuration signals would be tied HIGH or LOW, but they are configurable in the ARM1176JZF-S development chip. This enables you to test different build options.

Table 4.37. SYS-CFGDATA 1 register

Bits	Configuration signal	Reset Value	Description
[31:23]	Not used	-	Reserved for future use.
[22:21]	CFGSMMWCS7[1:0]	b10	SMC bank 7 data width: 00 = 8-bit 01 = 16-bit 10 = 32-bit 11 = undefined.
[20:19]	CFGSMCMEMRATIO[1:0]	b10	SMC AXI to external memory clock ratio: 00 = 1:1 01 = 2:1 10 = 3:1 11 = undefined.
[18]	CFGSMCAXIRATIO	0	SMC AXI sync down clock ratio: 0 = 1:1 1 = 2:1.
[17:15]	CFGAXIEXTRATIOMSTR[2:0]	b010	AXI external master clock ratio: 000 = 1:1 001 = 2:1 010 = 3:1 011 = 4:1 100 = 5:1 101 = 6:1 110 = 7:1 111 = 8:1.
[14:12]	CFGAXIEXTRATIOSLV[2:0]	b010	AXI external slave clock ratio: 000 = 1:1 001 = 2:1 010 = 3:1 011 = 4:1 100 = 5:1 101 = 6:1 110 = 7:1 111 = 8:1.
[11]	CFGAXIRATIO	0	AXI: Core clock ratio: 0 = 2:1 1 = 4:1.
[10]	CFGCP15SDISABLE	0	TZ write access disable
[9]	CFGUBITINIT	0	ARMv6 unaligned behavior
[8]	CFGBIGENDINIT	0	ARMv5 big endian behavior
[7]	CFGVINITHI	0	High exception vector location
[6]	CFGINITRAM	0	ITCM at `0x0` for data and instructions at reset
[5:4]	CFGREMAP[1:0]	b10	Defines boot memory map: 00 = normal memory 01 = AXI ROM 10 = SMC 11 = AXI master port.
[3:0]	CFGCOREID[3:0]	b0000	LS nibble of core ID[7:0]

Table 4.38. SYS-CFGDATA 2 register

Bits	Configuration signal	Reset Value	Description
[31:18]	Not used	-	Reserved for future use.
[17]	CFGCLKSTOPSBWFI	0	Selects whether the Clock is stopped to the L2CC and ETM during CPU STANDBYWFI State: 0 = clock is left free running 1 = clock is stopped.
[16]	CFGIEMSHUTDOWN	0	Selects the IEM subsystem to be powered down from reset: 0 = functional 1 = shutdown.
[15]	CFGIRQSOURCE	1	Selects the nIRQ, nFIQ source: 0 = external 1 = internal.
[14]	CFGPLLFIXEDDESKEW	1	Selects external clock feedback path for on chip clock deskew
[13]	CFGPLLFIXEDPLLEN	1	PLL Enable
[12]	CFGPLLFIXEDBYPASSEN	0	Bypass VCO
[11:9]	CFGPLLFIXEDN	b001	PLL input divider. Caution Do not modify. Use only the default value of b001.
[8:5]	CFGPLLFIXEDM	b0001	PLL feedback divider. Caution Do not modify. Use only the default value of b0001.
[4]	CFGPLLFIXEDVCORANGE	1	Selects VCO range: 1 >133MHz 0 <133MHz.
[3]	CFGPLL2BYPASS	0	Bypass PLL2 (used by IEM subsystem)
[2]	CFGPLL1BYPASS	0	Bypass PLL1 (used by IEM subsystem)
[1]	CFGPLLBYPASS	0	Bypass PLLFIXED (typically the main reference generator, PLLREFCLK is used directly for the core clock instead of the PLL output PLLFIXEDCLK.)
[0]	CFGPLLREFCLK	0	Use PLLREFCLK as the input reference for PLL1 and PLL2

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