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The Power Management Interface consists of the memory locations and registers listed in Table 4.13. All registers except PWR_CONTROL are read-only.
Table 4.13. Power Management Interface registers in the FPGA
| Register | Address | Description |
|---|---|---|
| PWR_CONTROL | 0x1001C000 | Enables RAM recording of voltage, current, and power. |
| PWR_VOLTAGE_CTL0 | 0x1001C010 | Present VDDCORE reading |
| PWR_VOLTAGE_CTL1 | 0x1001C014 | Present VSOC reading |
| PWR_VOLTAGE_CTL2 | 0x1001C018 | Present VDDRAM reading |
| PWR_VOLTAGE_CTL3 | 0x1001C01C | Present TPSENSE reading |
| PWR_VOLTAGE_CTL4 | 0x1001C020 | Present PWROK reading |
| PWR_VOLTAGE_AVG0 | 0x1001C030 | Average of VDDCORE over last 1024 readings |
| PWR_VOLTAGE_AVG1 | 0x1001C034 | Average of VSOC over last 1024 readings |
| PWR_VOLTAGE_AVG2 | 0x1001C038 | Average of VDDRAM over last 1024 readings |
| PWR_VOLTAGE_AVG3 | 0x1001C03C | Average of TPSENSE over last 1024 readings |
| PWR_MEMA | 0x1001C800-0x1001C8FF | Last 512 IEM memreq and corereqs |
| PWR_MEMB | 0x1001C900-0x1001C9FF | Last 512 VDDCORE readings |
| PWR_MEMC | 0x1001CA00-0x1001CAFF | Last 512 VDDCORE power readings |
| PWR_MEMD | 0x1001CB00-0x1001CBFF | Last 512 VSOC readings |
| PWR_MEME | 0x1001CC00-0x1001CEFF | Last 512 VSOC power readings |
| PWR_MEMF | 0x1001CD00-0x1001CDFF | Last 512 VDDRAM readings |
| PWR_MEMG | 0x1001CE00-0x1001CEFF | Last 512 VDDRAM power readings |
| APC control | 0x10102000-0x10102FFF | Reserved |
Setting the RAM Enable bit to 0 stops more data being recorded to the memories. This enables software to fix the history buffers for software analysis.
Table 4.14. PWR_CONTROL
| Bits | Access | Description |
|---|---|---|
| [31:1] | - | Reserved. Use read-modify-write to preserve value. |
| [0] | Read/write | Enables cyclic recording of data to mem areas. (power-on reset state is 1) |
Read the voltage and current for the supplies listed in Table 4.15:
Table 4.15. PWR_READx registers
| Register | Address | Description |
|---|---|---|
| PWR_VOLTAGE_CTL0 | 0x10010010 | Present VDDCORE reading |
| PWR_VOLTAGE_CTL1 | 0x10010014 | Present VSOC reading |
| PWR_VOLTAGE_CTL2 | 0x10010018 | Present VDDRAM reading |
| PWR_VOLTAGE_CTL3 | 0x1001001C | Present TPSENSE reading |
| PWR_VOLTAGE_CTL4 | 0x10010020 | Present PWROK reading |
Table 4.16. PWR_READx content
| Bits | Access | Description |
|---|---|---|
| [31:16] | Read only | Present current level (or TPSENSA voltage if PWR_VOLTAGE_CTL3) |
| [15:0] | Read only | Present voltage level (or TPSENSB voltage if PWR_VOLTAGE_CTL3) |
The reading from the register is relative and must be converted to an absolute value by the formula:
Voltage = (PWR_VOLTAGE_CTLx *18) / 655200
Read the average voltage and current for the supplies listed in Table 4.15:
Table 4.17. PWR_AVGx registers
| Register | Address | Description |
|---|---|---|
| PWR_VOLTAGE_AVG0 | 0x10010030 | Average of VDDCORE over last 1024 readings |
| PWR_VOLTAGE_AVG1 | 0x10010034 | Average of VSOC over last 1024 readings |
| PWR_VOLTAGE_AVG2 | 0x10010038 | Average of VDDRAM over last 1024 readings |
| PWR_VOLTAGE_AVG3 | 0x1001003C | Average of TPSENSE over last 1024 readings |
Table 4.18. PWR_AVGx content
| Bits | Access | Description |
|---|---|---|
| [31:16] | Read only | Read average current level (or TPSENSA voltage if PWR_VOLTAGE_AVG3) |
| [15:0] | Read only | Read average voltage level (or TPSENSB voltage if PWR_VOLTAGE_AVG3) |
The reading from the register is relative and must be converted to an absolute value by the formula:
Voltage = (PWR_VOLTAGE_AVGx *18) / 655200
There are seven 512x32bit block RAMs embedded into the power monitor that enable reading the last 512 values. It also records the relative power consumed (voltage * current). This enables very fast software analysis of historical power use.
The RAM at 0x1001C800 records the history
of requests from the PowerWise Interface. This enables the additional
comparison of historical power use against requests from the IEM
(and consequently the correlation between the two). See Table 4.15:
Table 4.19. PWR_MEMx registers
| Register | Address | Description |
|---|---|---|
| PWR_MEMA | 0x1001C800- 0x1001CFFF | Requests from the PowerWise Interface |
| PWR_MEMB | 0x1001D000- 0x1001D7FF | Last 512 VDDCORE readings |
| PWR_MEMC | 0x1001D800- 0x1001DFFF | Last 512 VDDCORE power readings |
| PWR_MEMD | 0x1001E000- 0x1001E7FF | Last 512 VSOC readings |
| PWR_MEME | 0x1001E800- 0x1001EFFF | Last 512 VSOC power readings |
| PWR_MEMF | 0x1001F000- 0x1001F7FF | Last 512 VDDRAM readings |
| PWR_MEMG | 0x1001F800- 0x1001FFFF | Last 512 VDDRAM power readings |
Table 4.20. PWR_MEMx content
| Bits | Access | Description |
|---|---|---|
| [31:16] | Read only | Reserved. |
| [15:0] | Read only | Voltage or power level |
The reading from the register is relative and must be converted
to an absolute value by Voltage = (PWR_MEMx *18) / 655200
| Copyright © 2007-2011 ARM Limited. All rights reserved. | ARM DUI 0425F |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Reference > Advanced Power Controller and Power Management Interface > Power Management Interface registers in the FPGA |