The bus status register at 0x10000080 returns the ID of the bus the access was made with.

For AXI busses the AXI port used to create the read appends its own ID bits for forwarded accesses from the matrix. This value is returned on a read. This enables you to determine through software which master the software is executing on, as each bus matrix that the access passes through adds additional ID information. If the top bits are 0, then the master must be either the only master, or the primary master through any bus matrices. A non-zero value indicates that some other masters are in the system that must instead be considered the primary master.

This register returning the RID bits onto the RDATA bus. Because there is a bus matrix inside the FPGA between the HDRX bus (six ID bits), and a local master (PCI), there are usually seven ID bits in use inside the FPGA.

Although this board typically only runs software on the ARM1176JZF-S, this register is maintained to enable software compatibility with the Emulation Baseboard and to enable operating multi-core systems without the requirement to change the baseboard FPGA image.