Chapter 4. Programmer’s Reference
This chapter describes the memory map and the configuration
registers for the peripherals in the ARM1176JZF-S development chip. It contains the
following sections:
Memory map
ARM1176JZF-S development chip system
controller
Advanced Power Controller and Power
Management Interface
Advanced Audio CODEC Interface, AACI
Character LCD display
Color LCD Controller, CLCDC
Dynamic Memory Controller, DMC
Ethernet
FPGA status and system control registers
General Purpose Input/Output, GPIO
Interrupt controllers in the ARM1176JZF-S
development chip
Interrupt controllers in the FPGA
Level 2 Cache Controller
Keyboard and Mouse
Interface, KMI
MultiMedia Card Interfaces, MCI
PCI controller
Real Time Clock, RTC
Serial bus interface
Smart Card Interface, SCI
Synchronous Serial Port, SSP
Synchronous Static Memory Controller,
SSMC
System Controller
Timers
TrustZone Protection Controller
USB interface
UART
Watchdog.
For detailed information on the programming interface for
ARM PrimeCell peripherals and controllers, see the appropriate technical
reference manual. For the interrupt signals and release versions
of ARM IP, see the section of this chapter that describes the peripheral.