Five programmable (6-200 MHz) clocks are supplied to the FPGA by the programmable MicroClock ICS307 clock generators (OSC0-OSC4):
- OSCCLK0
This is the reference clock for the CLCDC.
OSC0 uses a 24MHz crystal as its reference. A fixed-frequency 24MHz signal, REFCLK24MHZ, is output from OSC0 and used as a reference signal for:
The input for programmable oscillators OSC1-OSC4.
the Ethernet controller clock (the Ethernet serial data clock is generated from a 25MHz crystal on the Ethernet controller).
the USB controller clock
the USB debug controller clock
the external peripheral clocks for the SCI, UART, and SSP in the ARM1176JZF-S development chip.
the input to divide-by-24 logic in the FPGA that produces the 1MHz reference clock for the timers.
- OSCCLK 1
This is the reference for the ARM1176JZF-S development chip PLLREFCLK1. (This clock can be selected by the IEM system to reduce power consumption.)
- OSCCLK2
This is the reference for the ARM1176JZF-S development chip PLLREFCLK2. (This clock can be selected by the IEM system to reduce power consumption.)
- OSCCLK3
This is the reference for the ARM1176JZF-S development chip PLLREFCLK. This is the master reference clock used to generate the AXI clocks, APB clock, and the memory controller clocks. (If operating in 100% power mode with IEM off, this is also the reference for the core clock PLL.)
- OSCCLK4
This is the reference to the FPGA. (It is not used in the reference implementation.)
The output frequencies of the ICS307s are controlled by divider values loaded into the serial data input pins on the oscillators. The divider values are defined by the SYS_OSCx and SYS_OSCRESETx registers. The data stream and register format is shown in Figure 3.13. See Oscillator registers, SYS_OSCx for details on the clock control registers.
Note
Bit 23 is loaded into the shift register first and bit 0 is loaded last. Data is clocked into the ICS307DATA pins of the oscillators on the rising edge of ICS307CLK. One of the ICS307STRB[4:0] signals is pulsed HIGH to latch the serial data into the divider control register.
You can calculate the oscillator output frequency from the formula:
where:
- VDW
Is the VCO divider word (4 - 511) from SYS_OSCx[8:0]
- RDW
Is the reference divider word (1 - 127) from SYS_OSCx[15:9]
- DIVIDE
Is the divide ratio (2 to 10) selected from SYS_OSCx[18:16]:
b000selects divide by 10b001selects divide by 2b010selects divide by 8b011selects divide by 4b100selects divide by 5b101selects divide by 7b110selects divide by 3b111selects divide by 6.
For more information on the ICS clock generator and a frequency
calculator, see the ICS web site at www.icst.com.
For details of the clock control registers, see FPGA status and system control registers.
PDF version