Table 3.3 lists
the default levels of reset that results from external sources.
Table 3.3. Reset sources and effects
| External source | Reset level | Hardware nBOARDPOR generated | FPGA reloaded and Dev. Chip configured with default
values | Dev. Chip reconfigured from SYS_CFGDATA registers | Reset generated for CPU, memory and peripherals |
|---|
| Power on | 0 | Yes | Yes | Yes | Yes |
| FPGA CONFIG pushbutton | 1 | No | Yes | Yes | Yes |
| DEV CHIP RECONFIG pushbutton | 2 | No | No | Yes | Yes |
| RESET pushbutton or software reset | 3 | No | No | No | Yes |
See Reset signals for
a description of the reset signals on the Logic Tile headers.
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