2.2.4. FPGA image selection
The configuration switches S1-1 and S1-2 select the FPGA image
to be used by the PB1176JZF-S. If a Logic Tile is attached to the PB1176JZF-S,
S1-1 also selects the Logic Tile FPGA image by controlling FPGA_IMAGE at the tile stack. The default position
for both switches is OFF and image 0 located at address 0x0 is loaded.
For more information on loading new FPGA images see Appendix H Loading FPGA Images.
Table 2.4. FPGA image selection
| S1-2 | S1-1 | PB1176JZF-S FPGA image | Logic Tile FPGA image | PB1176JZF-S FPGA image address |
|---|
| OFF | OFF | FPGA image 1 (this is the image supplied with
the board) | 0 | 0x0 |
| OFF | ON | FPGA image 2 (not supplied) | 1 | 0x200000 |
| ON | OFF | FPGA image 3 (not supplied) | 0 | 0x400000 |
| ON | ON | FPGA image 4 (not supplied) | 1 | 0x600000 |
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