The clock domains for the PB1176JZF-S are shown in Figure 3.10.
Figure 3.10. Clock architecture for PB1176JZF-S
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.
The following sections describe:
FPGA Peripheral clocks
ARM1176JZF-S development chip clocks
ICS307 programmable clock generators
For details on Logic Tile clocks, see Appendix C RealView Logic Tile.