RealView® Platform Baseboard for ARM1176JZF-S User Guide


Table of Contents

About this book
Intended audience
Using this book
Product revision status
Typographical conventions
Other conventions
Further reading
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the PB1176JZF-S
1.1.1. Baseboard expansion
1.1.2. About the ARM1176JZF-S development chip
1.1.3. About the PB1176JZF-S FPGA
1.2. Precautions
1.2.1. Ensuring safety
1.2.2. Preventing damage
2. Getting Started
2.1. Setting up the PB1176JZF-S
2.2. Setting the configuration switches
2.2.1. Boot memory selection
2.2.2. Secure debug selection
2.2.3. Clock frequency selection
2.2.4. FPGA image selection
2.2.5. Default switch positions
2.2.6. LED indicators
2.2.7. Boot Monitor configuration
2.3. Connecting JTAG, Trace, and configuration equipment
2.3.1. ARM CoreSight
2.3.2. Connecting to the USB config port
2.3.3. Connecting the Trace Port Analyzer
2.4. Supplying power
3. Hardware Description
3.1. PB1176JZF-S architecture
3.1.1. PCB layout
3.1.2. System architecture
3.1.3. ARM1176JZF-S development chip
3.1.4. PB1176JZF-S FPGA
3.1.5. Displays
3.1.6. RealView Logic Tile expansion
3.1.7. Memory
3.1.8. Clock generators
3.1.9. Debug and test interfaces
3.2. ARM1176JZF-S development chip
3.2.1. ARM1176JZF-S development chip overview
3.2.2. Configuration control
3.2.3. AXI buses
3.2.4. Intelligent Energy Management
3.3. Development chip peripherals
3.3.1. Memory interface
3.3.2. CLCDC interface
3.3.3. GPIO interface
3.3.4. Interrupt controllers
3.3.5. Synchronous Serial Port, SSP
3.3.6. UART interface
3.4. FPGA peripherals
3.4.1. FPGA architecture
3.4.2. Character LCD controller
3.4.3. Advanced Audio Codec Interface, AACI
3.4.4. Keyboard/Mouse Interface, KMI
3.4.5. Memory Card Interface, MCI
3.4.6. Smart Card interface, SCI
3.4.7. Serial bus interface
3.4.8. User switches and LEDs
3.4.9. USB interface
3.4.10. PCI interface
3.4.11. Ethernet interface
3.5. FPGA configuration
3.6. Reset controller
3.6.1. Reset level
3.6.2. Memory aliasing at reset
3.7. Power supply
3.7.1. Reading the core and RAM voltages
3.8. Clock architecture
3.8.1. FPGA Peripheral clocks
3.8.2. ARM1176JZF-S development chip clocks
3.8.3. ICS307 programmable clock generators
3.9. Test, configuration, and debug interfaces
3.9.1. JTAG debug port and USB config port support
3.9.2. Integrated logic analyzer
3.9.3. Embedded trace support
4. Programmer’s Reference
4.1. Memory map
4.2. ARM1176JZF-S development chip system controller
4.2.1. SoCConfig1
4.2.2. SoCConfig2
4.2.3. System Control register
4.2.4. System Status register
4.2.5. DCG Index Mapping Registers
4.2.6. DCG Fractional Performance Level Mapping Registers
4.2.7. DVC Index Level Mapping Registers
4.2.8. Processor Frequency Configuration Register
4.2.9. PLLCFGPERFx, PLL Configuration Settings Registers
4.2.10. DCG System Status Register
4.2.11. AXI Priority Register
4.2.12. SMC Exclusive Access Monitor ID Register
4.2.13. DLL Calibrate Register
4.3. Advanced Power Controller and Power Management Interface
4.3.1. Power Management Interface registers in the FPGA
4.4. Advanced Audio CODEC Interface, AACI
4.4.1. PrimeCell Modifications
4.5. Character LCD display
4.6. Color LCD Controller, CLCDC
4.6.1. PrimeCell Modifications
4.6.2. Display resolutions and display memory organization
4.7. Dynamic Memory Controller, DMC
4.7.1. Register values
4.8. Ethernet
4.9. FPGA status and system control registers
4.9.1. ID Register, SYS_ID
4.9.2. Switch Register, SYS_SW
4.9.3. LED Register, SYS_LED
4.9.4. Oscillator registers, SYS_OSCx
4.9.5. Lock Register, SYS_LOCK
4.9.6. 100Hz Counter, SYS_100HZ
4.9.7. Configuration registers SYS_CFGDATAx
4.9.8. Flag registers, SYS_FLAGx and SYS_NVFLAGx
4.9.9. Reset Control Register, SYS_RESETCTL
4.9.10. PCI Control Register, SYS_PCICTL
4.9.11. Flash Control Register, SYS_FLASH
4.9.12. CLCD Control Register, SYS_CLCD
4.9.13. Boot Select Register, SYS_BOOTCS
4.9.14. 24MHz Counter, SYS_24MHZ
4.9.15. Miscellaneous System Control Register, SYS_MISC
4.9.16. Bus status registers, SYS_BUSID
4.9.17. System status registers, SYS_PROCIDx
4.9.18. Oscillator reset registers, SYS_OSCRESETx
4.9.19. Oscillator test registers, SYS_TEST_OSCx
4.10. General Purpose Input/Output, GPIO
4.11. Interrupt controllers in the ARM1176JZF-S development chip
4.11.1. Development chip TrustZone Interrupt Controller
4.11.2. Development chip GIC
4.11.3. Development chip interrupt signals
4.12. Interrupt controllers in the FPGA
4.12.1. FPGA interrupt signals
4.12.2. GIC Distribution register
4.12.3. GIC CPU Interface
4.12.4. GIC reserved register addresses
4.13. Level 2 Cache Controller
4.14. Keyboard and Mouse Interface, KMI
4.15. MultiMedia Card Interfaces, MCI
4.16. PCI controller
4.16.1. Control registers
4.16.2. PCI configuration
4.17. Real Time Clock, RTC
4.18. Serial bus interface
4.19. Smart Card Interface, SCI
4.20. Synchronous Serial Port, SSP
4.21. Synchronous Static Memory Controller, SSMC
4.21.1. Register values
4.22. System Controller
4.23. Timers
4.24. TrustZone Protection Controller
4.24.1. FPGA TrustZone Protection Controller registers
4.24.2. Development Chip TrustZone Protection Controller registers
4.25. UART
4.25.1. PrimeCell Modifications
4.26. USB interface
4.27. Watchdog
A. Signal Descriptions
A.1. Synchronous Serial Port interface
A.2. Smart Card interface
A.3. UART interface
A.4. USB interface
A.5. Audio CODEC interface
A.6. MMC and SD flash card interface
A.7. CLCD DVI display interface
A.8. GPIO interface
A.9. Keyboard and mouse interface
A.10. Ethernet interface
A.11. RealView Logic Tile header connectors
A.12. Test and debug connections
A.12.1. JTAG
A.12.2. USB debug port
A.12.3. Trace connector pinout
A.12.4. Integrated logic analyzer
B. Specifications
B.1. Electrical specification
B.1.1. Bus interface characteristics
B.1.2. Current requirements
B.2. Clock rate restrictions
B.3. Mechanical details
C. RealView Logic Tile
C.1. About the RealView Logic Tile
C.1.1. Variable I/O levels
C.1.2. AXI buses
C.1.3. JTAG
C.1.4. RealView Logic Tile clocks
C.1.5. Reset signals
C.2. Signals on the tile header connectors
C.2.1. HDRX signals
C.2.2. HDRY signals
C.2.3. HDRZ
D. PCI Backplane and Enclosure
D.1. Connecting the PB1176JZF-S to the PCI enclosure
D.1.1. Setting the backplane configuration switches
D.1.2. Connecting two PB1176JZF-S boards
D.2. Backplane hardware
D.2.1. JTAG signals
D.3. Connectors
D.3.1. Power connector
D.3.2. Logic analyzer connector
D.3.3. JTAG connector
E. Memory Expansion Boards
E.1. About memory expansion
E.1.1. Operation without expansion memory
E.1.2. Memory board configuration
E.2. Fitting a memory board
E.3. Connector pinout
E.3.1. Expansion connector
F. Boot Monitor and platform library
F.1. About the Boot Monitor
F.2. About the platform library
F.3. Using the baseboard Boot Monitor and platform library
F.3.1. Boot Monitor configuration switches
F.3.2. Running the Boot Monitor
F.3.3. Loading Boot Monitor into NOR flash
F.3.4. Redirecting character output to hardware devices
F.3.5. Using a boot script to run an image automatically
F.3.6. Rebuilding the Boot Monitor or platform library
F.3.7. Building an application with the platform library
F.3.8. Building an application that uses semihosting
F.3.9. Loading and running an application from NOR flash
F.3.10. Running an image from MMC or SD card
F.3.11. Using the Network Flash Utility
G. Boot Monitor Commands
G.1. About Boot Monitor commands
G.2. Boot Monitor command set
H. Loading FPGA Images
H.1. General procedure
H.2. Board files
H.2.1. Naming conventions for board files
H.2.2. Naming conventions for image files
H.3. The progcards utilities
H.4. Upgrading your hardware
H.4.1. Procedure for progcards_rvi.exe
H.4.2. Procedure for progcards_usb.exe
H.4.3. Troubleshooting

List of Figures

1. Key to timing diagram conventions
2.1. Location of S7, S1 and S6
2.2. JTAG, Trace, and config connectors
2.3. Power connectors
3.1. PB1176JZF-S layout
3.2. PB1176JZF-S block diagram
3.3. ARM1176JZF-S development chip block diagram
3.4. AXI master bus multiplexing
3.5. Memory devices
3.6. Interrupt controller block diagram
3.7. FPGA block diagram
3.8. PCI bridge
3.9. Voltage control and voltage and current monitoring
3.10. Clock architecture for PB1176JZF-S
3.11. Development chip clocks
3.12. DCG clock selection and divider logic
3.13. Serial data and SYS_OSCx register format
3.14. JTAG data paths in debug mode
3.15. JTAG data paths in debug mode with ILA
3.16. JTAG data paths in config mode
4.1. Memory map
4.2. PLLCFGPERFx registers
4.3. AACI ID register
4.4. ID Register, SYS_ID
4.5. SYS_SW
4.6. SYS_LED
4.7. Oscillator Register, SYS_OSCx
4.8. Lock Register, SYS_LOCK
4.10. SYS_CLCD
4.12. SYS_MISC
4.13. Oscillator Register, SYS_OSCRESETx
4.14. TZICFIQBypass Register bit assignments
4.15. TZICProtection Register bit assignments
4.16. TZICLockStatus Register bit assignments
4.17. TZICPeriphlD0-3 registers bit assignments
4.18. TZICPeriphlDO Register bit assignments
4.19. TZICPeriphlD1 Register bit assignments
4.20. TZICPeriphlD2 Register bit assignments
4.21. TZICPeriphlD3 Register bit assignments
4.22. TZICPCelllD0-3 Registers bit assignments
4.23. Distributor Register Control Register bit assignments
4.24. Interrupt Controller Type Register bit assignments
4.25. Interrupt Set-Enable Register 0 bit assignments
4.26. Interrupt Set-Enable Register 1 bit assignments
4.27. Interrupt Clear-Enable Register 0 bit assignments
4.28. Interrupt Clear-Enable Register 1 bit assignments
4.29. Interrupt Set-Pending Register 0 bit assignments
4.30. Interrupt Set-Pending Register 1 bit assignments
4.31. Interrupt Clear-Pending Register 0 bit assignments
4.32. Interrupt Clear-Pending Register 1 bit assignments
4.33. Active Bit Register 0 and 1 bit assignments
4.34. Interrupt Priority Register 0-3 bit assignments
4.35. Interrupt Priority Register 4-6 bit assignments
4.36. Interrupt Priority Register 7-15 bit assignments
4.37. Interrupt CPU Target Registers 0-6 bit assignments
4.38. Interrupt CPU Target Register 7 bit assignments
4.39. Interrupt CPU Target Register 8-15
4.40. Interrupt Configuration Register 0 bit assignments
4.41. Interrupt Configuration Register 1 bit assignments
4.42. Interrupt Configuration Register 2-3 bit assignments
4.43. Software Interrupt Register bit assignments
4.44. AXI M to PCI mapping
4.45. PCI_SELFID register
4.46. PCI_FLAGS register
4.47. PCI to AXI S mapping
4.48. PCI_SMAPx register
4.49. Secure and non-secure internal RAM
A.1. SSP expansion interface
A.2. Smartcard contacts assignment
A.3. SCI expansion connector J29
A.4. Serial connector for J26A, J26B, J27A, and J27B
A.5. USB interfaces
A.6. Audio connectors
A.7. AACI expansion connector
A.8. MMC/SD card socket pin numbering
A.9. MMC card
A.10. DVI Digital/Analog connector
A.11. GPIO connector
A.12. KMI connector
A.13. Ethernet connector J5
A.14. RealView Logic Tile HDRX, HDRY, and HDRZ pin numbering
A.15. Test points and debug connectors
A.16. JTAG connector J12
A.17. USB debug connector J15
A.18. AMP Mictor connector
A.19. Integrated logic analyzer connector J11
B.1. Baseboard mechanical details
C.1. AXI busses on Logic Tile
C.2. JTAG signals to Logic Tiles
C.3. Power-on reset and configuration timing
C.4. HDRX, HDRY, and HDRZ pin numbering
D.1. Installing the platform board into the PCI enclosure
D.2. Multiple boards on PCI bus
D.3. PCI backplane
D.4. JTAG signal flow on the PCI backplane
D.5. AMP Mictor connector J4
D.6. PCI expansion board JTAG connector J5
E.1. Static memory board block diagram
E.2. Samtec QSH 120-way static expansion connector

List of Tables

2.1. Selecting the boot device
2.2. Selecting secure debug
2.3. Clock frequency selection
2.4. FPGA image selection
2.5. Default switch position
2.6. LED Indicators
2.7. STDIO redirection
3.1. Serial interface signal assignment
3.2. Serial interface device addresses
3.3. Reset sources and effects
3.4. CFGREMAP signals
3.5. FPGA clocks
3.6. ARM1176JZF-S development chip clocks
3.7. ACLKEXTDIVSLV divisor values
3.8. ACLKEXTDIVMSTR divisor values
3.9. SMCMEMCLKDIV divisor values
3.10. JTAG related signals
4.1. Memory map
4.2. Development chip system controller registers
4.3. Configuration signals register
4.4. Configuration signals
4.5. System Control register
4.6. System Status register
4.7. PLL Configuration Settings register
4.8. Example formulas for PLLCFGPERFx registers
4.9. AXIPriority register
4.10. SMC Exclusive Access Monitor ID register
4.11. DLL Calibrate Outputs register
4.12. Power Management Interface and IEM Interface implementation
4.13. Power Management Interface registers in the FPGA
4.15. PWR_READx registers
4.16. PWR_READx content
4.17. PWR_AVGx registers
4.18. PWR_AVGx content
4.19. PWR_MEMx registers
4.20. PWR_MEMx content
4.21. AACI implementation
4.22. Modified AACI PeriphID3 register
4.23. Character LCD display implementation
4.24. Character LCD control and data registers
4.25. Character LCD display commands
4.26. CLCDC implementation
4.27. PrimeCell CLCDC register differences
4.28. Values for different display resolutions
4.29. DMC implementation
4.30. SDRAM register values
4.31. Ethernet implementation
4.32. Register map for FPGA System Controller registers
4.33. ID Register, SYS_ID bit assignment
4.34. Oscillator Register, SYS_OSCx bit assignment
4.35. Default values for oscillators
4.36. Lock Register, SYS_LOCK bit assignment
4.37. SYS-CFGDATA 1 register
4.38. SYS-CFGDATA 2 register
4.39. Flag registers
4.40. Reset level control
4.41. PCI bus status
4.42. Flash control
4.43. SYS_CLCD register
4.44. BOOT configuration switches
4.45. SYS_MISC
4.47. System status registers
4.48. Oscillator test registers
4.49. GPIO implementation
4.50. TZIC implementation in development chip
4.51. TZIC register summary
4.52. TZICFIQStatus Register bit assignments
4.53. TZICRawIntr Register bit assignments
4.54. TZICIntSelect Register bit assignments
4.55. TZICFIQEnable Register bit assignments
4.56. TZICFIQEnClear Register bit assignments
4.57. TZICFIQBypass Register bit assignments
4.58. TZICProtection Register bit assignments
4.59. TZICLock Register bit assignments
4.60. TZICLockStatus Register bit assignments
4.61. TZICPeriphlD0-3 Register bit assignments
4.62. TZICPeriphID0 Register bit assignments
4.63. TZICPeriphID1 Register bit assignments
4.64. TZICPeriphID2 Register bit assignments
4.65. TZICPeriphID3 Register bit assignments
4.66. TZICPCellID0 Register bit assignments
4.67. TZICPCellID1 Register bit assignments
4.68. TZICPCellID2 Register bit assignments
4.69. TZICPCellID3 Register bit assignments
4.70. GIC implementation in development chip
4.71. Interrupt signals to development chip interrupt controllers
4.72. GIC implementation in FPGA
4.73. Interrupt signals to FPGA primary and secondary GICs
4.74. FPGA Register summary
4.75. Distributor Register Control Register bit assignments
4.76. Interrupt Controller Type Register bit assignments
4.77. Interrupt Set-Enable Register 0 bit assignments
4.78. Interrupt Set-Enable Register 1 bit assignments
4.79. Interrupt Clear-Enable Register 0 bit assignments
4.80. Interrupt Clear-Enable Register 1 bit assignments
4.81. Interrupt Set-Pending Register 0 bit assignments
4.82. Interrupt Set-Pending Register 1 bit assignments
4.83. Interrupt Clear-Pending Register 0 bit assignments
4.84. Interrupt Clear-Pending Register 1 bit assignments
4.85. Active Bit Register 0 and 1 bit assignments
4.86. Interrupt Priority Register 0-3 bit assignments
4.87. Interrupt Priority Register 4-6 bit assignments
4.88. Interrupt Priority 7-15 Register bit assignments
4.89. Interrupt CPU Target Registers 0-6 bit assignments
4.90. Interrupt CPU Target Register 7 bit assignments
4.91. Interrupt CPU Target Register 8-15 bit assignments
4.92. Interrupt Configuration Register 0 bit definition
4.93. IT[0] interrupt definition encoding
4.94. IT[1] interrupt definition encoding
4.95. Interrupt Configuration Register 1 bit assignments
4.96. Interrupt Configuration Register 2-3 bit definition
4.97. Software Interrupt Register bit definition
4.98. CPU interface registers
4.99. CPU Interface Control register bit assignments
4.100. Priority Mask Register bit assignments
4.101. Binary Pointer Register bit assignments
4.102. Binary Point value meanings
4.103. Interrupt Acknowledge Register bit assignments
4.104. End of Interrupt Register bit assignments
4.105. Running interrupt Register bit assignments
4.106. Highest Pending interrupt Register bit assignments
4.107. L2CC implementation in development chip
4.108. KMI implementation
4.109. MCI implementation
4.110. PCI controller implementation
4.111. PCI bus memory map for AXI M bridge
4.112. PCI controller registers
4.113. PCI_IMAP0 register format
4.114. PCI_IMAP1 register format
4.115. PCI_IMAP2 register format
4.116. PCI_SELFID register format
4.117. PCI_FLAGS register format
4.118. PCI_SMAPx register format
4.119. PCI backplane configuration header addresses (self-config)
4.120. PCI backplane configuration header addresses (normal configuration)
4.121. PCI configuration space header
4.122. PCI bus commands supported
4.123. RTC implementation
4.124. Serial bus implementation
4.125. Serial bus register
4.126. Serial bus device addresses
4.127. SCI implementation
4.128. SSP implementation
4.129. SSMC implementation
4.130. Register values for NOR2
4.131. Register values for Intel flash, standard async read mode, no bursts
4.132. Register values for Intel flash, async page mode
4.133. Register values for Samsung SRAM
4.134. Register values for Spansion BDS640
4.135. Register values for Spansion LV256
4.136. System controller implementation
4.137. Timer implementation
4.138. TrustZone Protection Controller implementation
4.139. FPGA TrustZone Protection Controller registers
4.140. FPGA TZPCDECPROT0x bit assignment
4.141. FPGA TZPCDECPROT1x bit assignment
4.142. FPGA TZPCDECPROT2 register
4.143. Development chip TrustZone Protection Controller registers
4.144. Development chip TZPCDECPROT0x bit assignment
4.145. Development chip TZPCDECPROT1x bit assignment
4.146. Development chip TZPCDECPROT2
4.147. UART implementation
4.148. USB implementation
4.149. USB controller base address
4.150. Watchdog implementation
A.1. SSP signal assignment
A.2. Smartcard connector signal assignment
A.3. Signals on SCI expansion connector
A.4. Serial plug signal assignment
A.5. USB signals
A.6. Audio CODEC expansion connector signals
A.7. Multimedia Card interface signals
A.8. DVI Digital/Analog connector signals
A.9. Mouse and keyboard port signal descriptions
A.10. Ethernet signals
A.11. Trace connector J2
A.12. Trace connector J3
A.13. Logic Tile trace connector J7
B.1. PB1176JZF-S electrical characteristics
B.2. Current requirements from DC IN (12V)
B.3. Current requirements from terminal connector
B.4. Maximum current load on supply voltage rails
C.1. RealView Logic Tile clock signals
C.2. Reset signal descriptions
C.3. HDRX signals
C.4. HDRY signals
C.5. HDRZ signals
D.1. LED indicators
D.2. Configuration switches
D.3. Power and reset switches
D.4. Test points
D.5. ATX power connector
D.6. Mictor connector pinout
E.1. Static memory connector signals
F.1. STDIO redirection
F.2. platform library options
F.3. NFU commands
F.4. NFU MANAGE commands
G.1. Standard Boot Monitor command set
G.2. MMC and SD card sub-menu commands
G.3. Boot Monitor Configure commands
G.4. Boot Monitor Debug commands
G.5. Boot Monitor NOR flash commands

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

The system should be powered down when not in use.

The ARM1176JZF-S generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • ensure attached cables do not lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment and the receiver

  • connect the equipment into an outlet on a circuit different from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technician for help


It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision ANovember 2007First release.
Revision BMarch 2008Second release to change memory map and TZ content.
Revision CJune 2008Third release to provide more information on interrupt controllers, power control, and protection control.
Revision DJanuary 2009Fourth release to correct errata.
Revision EMarch 2010Fifth release to correct errata.
Revision FApril 2011Sixth release to correct errata.
Copyright © 2007-2011 ARM Limited. All rights reserved.ARM DUI 0425F