7.4. Example SOPC system clocking

For high-performance designs, a faster clock might be necessary to drive the internal logic.

Changes in the clock frequency might require changes to the external SRAM PLL, and to the number of wait states necessary for the external flash. If an SDRAM is implemented, it is also affected by an input clock frequency change. The configuration changes are generally quite technical, and highly dependent on the specific development board. Your local Altera FAE can provide relevant characterizations for the Cyclone III Starter Board.

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