8.1.2. Step 2: Configure the system

Launch SOPC Builder by selecting Tools → SOPC Builder from the menu. This is the tool you must use to build the Cortex-M1 based system, including the testbench.

Enter CortexM1_ExampleDesign in the Create New System dialog as shown in Figure 8.7.

Figure 8.7. SOPC Builder Create New System dialog

SOPC Builder Create New System dialog

Click OK.

The Cortex-M1 component must be added onto the IP Search Path as described in the Cortex-M1 FPGA Development Kit Installation Guide.

Add the ARM Cortex-M1 processor component by selecting the component from the tree view on the left side of the SOPC Builder window and click Add as shown in Figure 8.8.

Figure 8.8. Initial SOPC Builder screen

Initial SOPC Builder screen

The ARM Cortex-M1 Processor settings window appears as shown in Figure 8.9.

Configure the processor with following parameters:

Figure 8.9. ARM Cortex-M1 Processor settings window

ARM Cortex-M1 Processor settings window

Click Finish.

You have instantiated the Cortex-M1 component in the example SOPC system design, as shown in Figure 8.10. Rename the Cortex-M1 component to arm_cortexm1_inst by right-clicking on the instantiated component and selecting Rename.

Figure 8.10. Processor instantiation in SOPC Builder

Processor instantiation in SOPC Builder

Add a parallel IO block that connects to the bank of four LEDs on the Cyclone III Starter Board.

Select the PIO (Parallel I/O) block from the tree view on the left, as shown in Figure 8.10, and click Add.

The dialog window in Figure 8.11 appears.

Configure the width of the PIO port to be 4. This corresponds to the four LEDs on the starter board. The remaining configurations are defaults.

Figure 8.11. LED IF component parameter settings dialog

LED IF component parameter settings dialog

Click Finish.

You have added the PIO module for the LEDs to the system. Make the following configurations:

Figure 8.12 shows the system after these configuration changes.

Figure 8.12. LED_IF component instantiated in SOPC Builder

LED_IF component instantiated in SOPC Builder

You must add another PIO component for the bank of four user switches on the starter board.

Configure the PIO as follows:

Click Finish on the configuration dialog window to instantiate the Switch PIO block.

In the SOPC Builder, set :

Connect the Switch_IF slave interface to the Cortex-M1 master interface by clicking in the Connection column next to the Switch_IF. Figure 8.13 shows the SOPC configuration window after you have added the Switch_IF.

Figure 8.13. Switch_IF component instantiated in SOPC Builder

Switch_IF component instantiated in SOPC Builder

Add an Interval Timer to the system.

Select the Interval Timer component from the tree view on the left side of the SOPC Builder window.

Click Add.

Keep the default settings in the configuration dialog and click Finish.

Make the following configuration changes to the instantiated timer:

Note

The timer has an interrupt output that is automatically connected to IRQ input vector (location 0) of the processor.

Figure 8.14 shows the SOPC configuration after you have added the Timer.

Figure 8.14. Timer component instantiated in SOPC Builder

Timer component instantiated in SOPC Builder

Add a JTAG UART to the system. Select the JTAG UART component from the tree view on the left side of the SOPC Builder window.

Click Add.

Keep the default settings, in the configuration dialog, and click Finish.

Make the following configuration changes to the instantiated UART:

The UART has an interrupt output that is automatically connected to IRQ input vector (location 1) of the ARM Cortex-M1 processor.

Figure 8.15 shows the SOPC configuration window after you have added the JTAG_UART.

Figure 8.15. JTAG_UART component instantiated in SOPC Builder

JTAG_UART component instantiated in SOPC Builder

Add a PLL module. The only purpose is to generate a phase-shifted output clock that connects to the external SSRAM chip on the board. You can configure the PLL to compensate for off-chip clock skew. The Cyclone III Starter Board has been characterized for a 50MHz clock and a clock phase shift of -3.3ns is required.

In the PLL configuration dialog window, click the Launch Altera's ALTPLL MegaWizard button. See Figure 8.16.

Figure 8.16. Launch PLL MegaWizard

Launch PLL MegaWizard

The first MegaWizard dialog window appears, as shown in Figure 8.17. Check that the input clock is set to 50MHz. This is the frequency of the on-board oscillator.

Figure 8.17. PLL parameter settings

PLL parameter settings

Click the Inputs/Lock tab and select Create 'locked' output, as shown in Figure 8.18. The locked output is connected to the system reset in the top level of the design.

Figure 8.18. PLL Lock output setting

PLL Lock output setting

Click the Output Clocks tab, and set Clock Phase shift to -3.33ns, as shown in Figure 8.19.

Figure 8.19. PLL Output Clocks setting

PLL Output Clocks setting

Click Finish to exit the PLL configuration dialog then click Finish to exit status dialog.

PLL MegaWizard configurations are now complete. Click Finish in the PLL dialog to complete the PLL instantiation in SOPC Builder.

Figure 8.20 shows the SOPC configuration after you have added the PLL.

Make the following configuration changes to the instantiated PLL:

Figure 8.20. PLL instantiated in SOPC Builder

PLL instantiated in SOPC Builder

Add a System ID peripheral. Select the System ID Peripheral from the tree view on the left and click Add. There are no configurations to make for the System ID Peripheral.

Click Finish on the dialog box.

Make the following configuration changes to the instantiated System ID:

Figure 8.21 shows the SOPC configuration after you have added the System ID.

Figure 8.21. System ID instantiated in SOPC Builder

System ID instantiated in SOPC Builder

Add a Flash Memory peripheral. Select the Flash Memory (CFI) from the tree view on the left side of the SOPC Builder window.

Click Add.

On the configuration dialog, change the Presets field to Intel 128P30, as shown in Figure 8.22. This corresponds to the Flash chip on the Cyclone III Starter Board.

Figure 8.22. Flash settings

Flash settings

Click Finish.

Make the following configuration changes to the Flash Memory peripheral:

Note

This base address is in memory space, not peripheral space for the processor.

Add a SSRAM Memory peripheral. Select Cypress CY7C1380C SSRAM from the tree view on the left side of the SOPC configuration window.

Click Add.

On the SSRAM configuration dialog, change the Memory size (MBytes) to 1, as shown in Figure 8.23. This corresponds to the size of the SSRAM memory on the Cyclone III Starter Board.

Figure 8.23. SSRAM settings dialog

SSRAM settings dialog

Click Finish.

Make the following configuration changes to the SSRAM:

Note

This base address is in memory space, not peripheral space for the processor.

To connect the external resources such as Flash and SSRAM to the System Interconnect Fabric, you must instantiate an Avalon-MM Tristate Bridge component. This component acts as a slave device to the System Interconnect Fabric and as a master to the external resources.

To add an Avalon-MM Tristate Bridge component, select the Avalon-MM Tristate Bridge component from the tree view on the left side of the SOPC configuration window and click Add.

On the Avalon MM Tristate Bridge dialog, keep the default settings as shown in Figure 8.24.

Figure 8.24. Tristate Bridge settings dialog

Tristate Bridge settings dialog

Click Finish.

You must make the connections to the SSRAM and flash components as shown in Figure 8.25.

Make the following configurations to the Tristate Bridge:

Figure 8.25. Tristate Bridge connections to SSRAM and flash

Tristate Bridge connections to SSRAM and flash

Note

You must connect the Tristate Bridge Avalon slave port to the ARM Cortex-M1 Processor Master port, and its Tristate Master port to the Flash and the SSRAM modules.

Edit the configuration settings by right-clicking on the module name and selecting Edit.

Note

This brings up the dialog configured in an earlier step.

Click Next.

On the Cyclone III Starter Board, the external FLASH and external SSRAM share the same address bus. Indicate this by selecting both address check boxes. See Figure 8.26.

Figure 8.26. Tristate Bridge connection settings dialog

Tristate Bridge connection settings dialog

Click Finish.

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