5.1. Generated SOPC HDL testbench

SOPC Builder generates the entire example SOPC system HDL, Cortex-M1 processor and subsystem, in addition to the simulation environment. However, SOPC Builder does not generate any software tests for the example SOPC system. This is the function of RealView MDK. The simulation environment, including simulation scripts, is contained in the directory CortexM1_ExampleDesign_sim, which is in the ExampleDesign directory of the Cortex-M1 FPGA Development Kit installation.

The simulation uses the HDL generated from SOPC Builder for the FPGA, the Altera Cyclone III primitive library models, external memory models, and testbench code.

Note

Because the SOPC Builder testbench only simulates the SOPC Builder-generated subsystem, the FPGA top level, CortexM1_ExampleDesign_Top.v, is not required for the simulation. It is only required for the FPGA synthesis.

The external memory models are in the simulation directory. The testbench HDL code is contained in the SOPC top level file ExampleDesign\CortexM1_ExampleDesign.v in the Cortex-M1 FPGA Development Kit installation directory. This file appears after the SOPC system is generated.

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