2.6.1. Generating the environment

The example design in the Cortex-M1 Development Kit is shipped without any automatically generated Verilog source output from SOPC Builder. Verilog source for the example SOPC system is required for simulation. You can generate the Verilog source from the included project files.


It is not possible to run an evaluation version of the processor in simulation. If you generate simulation files for an evaluation version, you will receive an error when you run the simulation.

It is not necessary to regenerate the entire FPGA system to load the design into the FPGA. The FPGA programming files are included in the kit.

Open the example Quartus II Project

Open Quartus II IDE, and select File → Open Project.

The Open Project dialog window appears as shown in Figure 2.10. Browse to the installed directory and select CortexM1_ExampleDesign.qpf.

Figure 2.10. CortexM1_ExampleDesign.qpf


Click Open.

Generate the SOPC system

Open SOPC Builder by selecting Tools → SOPC Builder.

Click Generate located at the bottom of the SOPC Builder window. See Figure 2.11.

Figure 2.11. Generate the example SOPC system

Generate the example SOPC system

The example SOPC system is generated. You can now simulate the system. You can also regenerate the FPGA programming files.


It is not necessary to regenerate the FPGA programming files. These are provided in the kit.

Regenerate the FPGA design (optional)

In the Quartus II window, select Processing → Start Compilation. This starts the following sequence:

  • compilation

  • synthesis

  • fitting (place-and-route)

  • assembly (programming file generation)

  • timing analysis.

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