1.2.2. Cortex-M1 processor SOPC Builder component

The processor is implemented with an Avalon memory-mapped bus master interface to connect to the System Interconnect Fabric.

The processor component provides debug and non-debug options, selected using the SOPC builder tools.

See the Cortex-M1 FPGA Development Kit Altera Cyclone III Edition Cortex-M1 User Guide for more details about the processor and its configuration options.

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