RealView Platform Baseboard Explore for Cortex-A9 User Guide: 4.3.20. Serial data register, SYS_SERIAL

4.3.20. Serial data register, SYS_SERIAL_DATA

The SYS_SERIAL_DATA register at 0x1000007C sets the Cortex-A9 structured ASIC serial configuration stream values.

This register holds the data to be sent or read from the A9 daughterboard through a serial stream. For a write, after the register has been updated, the contents are sent to the A9 daughterboard to the address described in the register SYS_SERIAL_ADDR. When reading this register, a pulse is generated after a read is issued at the address described in SYS_SERIAL_ADDR, The serial stream is sent from the A9 daughterboard and updates the contents of this register. However, the contents of the register are only updated after the first read is issued. Therefore, to read the updated contents of the serial stream, this register needs to be read from twice.

By default, the updated contents of the serial register on the A9 daughterboard is retained if a software or push button reset be issued.

Figure 4.21 shows the register bit assignment.

Figure 4.21. SYS_SERIAL_DATA register

Table 4.22 lists the function of the register bits.

Table 4.22. SYS_SERIAL_DATA register bit assignments

Bits	Access	Name	Reset	Description
[31:29]	Read/Write Lockable	CFGNMFI[2:0}	`b000`	Configures fast interrupts to be nonmaskable:0 = clear the NMFI bit in the CP15 c1 Control Register1 = set the NMFI bit in the CP15 c1 Control Register. CFGNMFI[x] configures fast interrupts to be nonmaskable for CPU[x].
[28:25]	Read/Write Lockable	CP15SDISABLE[3:0]	`b0000`	Disables write access to some system control processor registers. CP15SDISABLE[x] Disables write access to some system control processor registers in CPU[x]. See Cortex-A9 Technical Reference Manual (DDI 0388) for details of the affected registers.
[24]	Read/Write Lockable	−	`b0`	Reserved
[23:20]	Read/Write Lockable	CFGBIGEND_CPU[3:0]	`b0000`	Endianness configuration. Forces the EE bit in the CP15 c1 Control Register (SCTLR) to 1 at reset so that the Cortex-A9 processor boots with big-endian data handling.0 = EE bit is LOW1 = EE bit is HIGH CFGBIGEND_CPU[x] configures endianness for CPU[x].
[19]	Read/Write Lockable	SPNIDEN	`b1`	Secure privileged noninvasive debug enable for all CPUs:0 = not enabled1 = enabled.
[18]	Read/Write Lockable	SPIDEN	`b1`	Secure privileged invasive debug enable:0 = not enabled1 = enabled.
[17]	Read/Write Lockable	NIDEN	`b1`	Noninvasive debug enable fro all CPUs:0 = not enabled1 = enabled.
[16]	Read/Write Lockable	DBGEN	`b1`	Invasive debug enable fro all CPUs:0 = not enabled1 = enabled.
[15:12]	Read/Write Lockable	THUMBINIT[3:0]	`b0000`	Default exception handling state. When set to:0 = ARM1 = Thumb THUMBINIT[x] sets the default exception handling state for CPU[x].
[11:8]	Read/Write Lockable	VINITHI[3:0]	`b0000`	Controls the location of the exception vectors at reset:0 = start exception vectors at address `0x00000000`1 = start exception vectors at address `0xFFFF0000`. VINITHI[x] controls the location of the exception vectors at reset for CPU[x].
[7:4]	Read/Write Lockable	CLUSTERID	`b0000`	Value read in Cluster ID register field, bits[11:8] of the MPIDR. See Cortex-A9 Technical Reference Manual (DDI 0388) for details of the MPIDR register.
[3]	Read/Write Lockable	−	`b0`	Reserved
[2:0]	Read/Write Lockable	REMAP	`b000`	Remaps the lower 256MB of DDR2 memory on the daughterboard. SeeTable 4.23 for remap details.

Table 4.23. Daughterboard DDR2 memory remap

REMAP Value	Daughterboard DDR2 (Lower 256MB)	Baseboard DDR (lower 256MB)	Notes
`b000`	`0x20000000- 0x2FFFFFFF`	`0x00000000- 0x0FFFFFFF`	Lower 256MB of baseboard DDR memory at `0x70000000-0x7FFFFFFF` is aliased at `0x0000000-0x0FFFFFFF`
`b001`	`0x00000000- 0x0FFFFFFF`	`0x70000000- 0x7FFFFFFF`	Lower 256MB of daughterboard DDR2 memory at `0x20000000-0x2FFFFFFF` is aliased at `0x0000000-0x0FFFFFFF`.
`b010`	−	−	Reserved for Coherency Port validation.
`b100`	−	−	Reserved for Coherency Port validation.

Copyright © 2009-2011 ARM Limited. All rights reserved.	ARM DUI 0440B
Non-Confidential	ID060911
PDF version