RealView® Platform Baseboard Explore for Cortex™-A9 User Guide

HBI-0182 (baseboard) and HBI0183 (daughterboard)


Table of Contents

Preface
About this book
Intended audience
Using this book
Product revision status
Typographical conventions
Other conventions
Further reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. Precautions
1.1.1. Ensuring safety
1.1.2. Preventing damage
1.2. About the PBX-A9 baseboard
1.2.1. Cortex-A9 structured ASIC
1.2.2. Northbridge
1.2.3. Southbridge
1.2.4. PBX-A9 expansion
2. Getting Started
2.1. Setting up the baseboard
2.2. Boot Monitor configuration
2.3. JTAG, USB config, and Trace support
2.3.1. JTAG debugger
2.3.2. USB config port
2.3.3. Connecting the Trace Port Analyzer
2.4. Baseboard configuration switches
2.4.1. Boot memory configuration
2.4.2. Flash recovery
3. Hardware Description
3.1. Baseboard architecture
3.1.1. Bypassing the power switch
3.1.2. System architecture
3.1.3. Cortex-A9 test chip
3.1.4. Northbridge
3.1.5. Southbridge
3.1.6. PCI bus connectors
3.1.7. Displays
3.1.8. Logic Tile expansion
3.1.9. Clock generation
3.1.10. Debug and test interfaces
3.2. Tile interconnections
3.2.1. AXI bus multiplexing
3.3. Cortex-A9 structured ASIC with dual core, PBXA9-BD-0241A
3.4. Northbridge
3.4.1. Cortex-A9 structured ASIC interface
3.4.2. CLCD controller
3.4.3. Memory controllers
3.4.4. Multiplexed AHB-Lite interface
3.4.5. Multiplexed AXI interfaces
3.4.6. PCI interface
3.5. Southbridge peripherals
3.5.1. Reset controller
3.5.2. CompactFlash
3.5.3. APB peripherals
3.6. Ethernet interface
3.7. USB Interface
3.8. DVI Interface
3.9. PCI interface
3.10. Clock architecture
3.10.1. ICS307 programmable clock generators
3.10.2. Southbridge clocks
3.11. Resets
3.12. Interrupts
3.12.1. Cortex-A9 structured ASIC interrupt controller
3.12.2. PBX-A9 Southbridge interrupt controllers
3.12.3. Interrupt Controller routing
3.13. Test, configuration, and debug interfaces
3.13.1. Debug and Config port support
3.13.2. Integrated logic analyzer (ILA)
3.13.3. Embedded trace support
4. Programmer’s Reference
4.1. Memory map
4.2. Configuration and initialization
4.2.1. Remapping of boot memory
4.2.2. Memory characteristics
4.3. Status and system control registers
4.3.1. ID Register, SYS_ID
4.3.2. User Switch Register, SYS_USERSW
4.3.3. LED Register, SYS_LED
4.3.4. Oscillator Registers, SYS_OSCx
4.3.5. Lock Register, SYS_LOCK
4.3.6. 100Hz Counter, SYS_100HZ
4.3.7. Flag Registers, SYS_FLAGSx and SYS_NVFLAGSx
4.3.8. Reset Control Register, SYS_RESETCTL
4.3.9. MCI Register, SYS_MCI
4.3.10. Flash Control Register, SYS_FLASH
4.3.11. CLCD Control Register, SYS_CLCD
4.3.12. Configuration select switch, SYS_CFGSW
4.3.13. 24MHz Counter, SYS_24MHZ
4.3.14. Miscellaneous flags, SYS_MISC
4.3.15. DMA peripheral map register, SYS_DMAPSR
4.3.16. PCI Express status register, SYS_PEX_STAT
4.3.17. PCI status register, SYS_PCI_STAT
4.3.18. Control register 1, SYS_CTRL1
4.3.19. Control register 2, SYS_CTRL2
4.3.20. Serial data register, SYS_SERIAL_DATA
4.3.21. Serial address register, SYS_SERIAL_ADDR
4.3.22. Processor ID register 0, SYS_PROCID0
4.3.23. Processor ID register 1, SYS_PROCID1
4.3.24. Oscillator reset registers, SYS_OSCRESETx
4.3.25. Oscillator test registers, SYS_TEST_OSCx
4.4. System Controller (SYSCTRL)
4.4.1. PrimeCell modifications
4.5. Advanced Audio CODEC Interface, AACI
4.5.1. PrimeCell Modifications
4.6. Color LCD Controller, CLCDC
4.6.1. Display resolutions and display memory organization
4.7. Single Master Direct Memory Access Controller, SMDMAC
4.7.1. DMAC flow control
4.7.2. DMA channel allocation
4.8. DAP memory map
4.9. Dynamic Memory Controller, DMC
4.9.1. Register values
4.10. DDR2 Dynamic Memory Controller, DMC
4.11. Ethernet
4.12. General Purpose Input/Output, GPIO
4.12.1. Onboard I/O control
4.13. Generic Interrupt Controller, GIC
4.13.1. Generic interrupt controller registers
4.13.2. Handling interrupts
4.14. Keyboard and Mouse Interface, KMI
4.15. MultiMedia Card Interface, MCI
4.16. AXI to PCI and PCI to PCIx bridges
4.17. Real Time Clock, RTC
4.18. Two-wire serial bus interface, SBCon
4.19. Smart Card Interface, SCI
4.20. Synchronous Serial Port, SSP
4.21. Static Memory Controller, SMC
4.22. Timers
4.23. UART
4.24. USB interface
4.25. Watchdog
4.26. CompactFlash interface
4.26.1. CompactFlash Control Register, CF_CTRL
A. Signal Descriptions
A.1. CompactFlash interface
A.2. Audio CODEC interface
A.3. MMC and SD card interface
A.4. Keyboard and mouse interface
A.5. GPIO interface
A.6. UART interface
A.7. Synchronous Serial Port interface
A.8. Smart Card interface
A.9. Ethernet interface
A.10. USB interface
A.11. DVI display interface
A.12. RealView Logic Tile header connectors
A.12.1. HDRX signals
A.12.2. HDRY signals
A.12.3. HDRZ signals
A.13. Test and debug connections
A.13.1. JTAG
A.13.2. USB config port
A.13.3. Integrated Logic Analyzer (ILA)
A.13.4. Trace connector
B. Specifications
B.1. Electrical Specification
B.1.1. Bus interface characteristics
B.2. Timing specifications
B.2.1. Clock frequency restrictions
B.2.2. AXI bus timings
C. RealView Logic Tile Expansion
C.1. About the RealView Logic Tile
C.2. Header connectors
C.2.1. Variable I/O levels
C.2.2. RealView Logic Tile clock
C.2.3. JTAG
C.2.4. AXI buses used by the Northbridge and RealView Logic Tiles
C.2.5. Reset
D. Boot Monitor and platform library
D.1. About the Boot Monitor
D.2. About the platform library
D.3. Using the baseboard Boot Monitor and platform library
D.3.1. Boot Monitor configuration switches
D.3.2. Running the Boot Monitor
D.3.3. Loading Boot Monitor into NOR flash
D.3.4. Redirecting character output to hardware devices
D.3.5. Using a boot script to run an image automatically
D.3.6. Rebuilding the Boot Monitor or platform library
D.3.7. Building an application with the platform library
D.3.8. Building an application that uses semihosting
D.3.9. Loading and running an application from NOR flash
D.3.10. Running an image from MMC or SD card or CompactFlash
D.3.11. Using the Network Flash Utility
E. Boot Monitor Commands
E.1. About Boot Monitor commands
E.2. Boot Monitor command set
F. Loading FPGA Images
F.1. General procedure
F.2. Board files
F.2.1. Naming conventions for board files
F.2.2. Naming conventions for image files
F.3. The progcards utilities
F.4. Upgrading your hardware
F.4.1. Procedure for progcards_rvi.exe
F.4.2. Procedure for progcards_usb.exe
F.4.3. Troubleshooting
F.5. Loading PLD images
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. PBX-A9 system architecture
3.1. Baseboard layout
3.2. Front panel layout
3.3. Rear panel layout
3.4. PBX-A9 top level block diagram
3.5. Overview of bus routing in baseboard and tile
3.6. Top-level view of Cortex-A9 dual core structured ASIC and daughterboard
3.7. Northbridge block diagram
3.8. Southbridge block diagram
3.9. DVI output
3.10. PCI-PCI Express interface
3.11. Northbridge clock domains
3.12. Reset sequence
3.13. External and internal interrupt routing
3.14. Interrupt priority calculation
4.1. System memory map for standard peripherals
4.2. Memory map for Cortex-A9 structured ASIC peripherals
4.3. SYS_ID register
4.4. SYS_USERSW register
4.5. SYS_LED register
4.6. SYS_OSCx register
4.7. SYS_LOCK register
4.8. SYS_100HZ register
4.9. SYS_RESETCTL register
4.10. SYS_MCI register
4.11. SYS_FLASH register
4.12. SYS_CLCD register
4.13. SYS_CFGSW register
4.14. SYS_24MHZ register
4.15. SYS_MISC register
4.16. SYS_DMAPSR register
4.17. SYS_PEX_STAT register
4.18. SYS_PCI_STAT register
4.19. SYS_CTRL1 register
4.20. SYS_CTRL2 register
4.21. SYS_SERIAL_DATA register
4.22. SYS_SERIAL_ADDR register
4.23. SYS_PROCID0 register
4.24. SYS_PROCID1 register
4.25. SYS_OSCRESETx register
4.26. AACI ID register
4.27. CPU control register
4.28. Priority mask register
4.29. Binary point register
4.30. Binary point example
4.31. Interrupt acknowledge register
4.32. End of interrupt register
4.33. Running interrupt register
4.34. Highest pending interrupt register
4.35. Distributor control register
4.36. Controller type register
4.37. Set-enable1 register
4.38. Set-enable2
4.39. Clear-enable1 register
4.40. Clear-enable2 register
4.41. Set-pending1 register
4.42. Set-pending2 register
4.43. Clear-pending1 register
4.44. Clear-pending2 register
4.45. Active1 register
4.46. Active2 register
4.47. Priority register
4.48. CPU targets register
4.49. Configuration register
4.50. Software interrupt register
4.51. CF_CTRL Register
A.1. CompactFlash connector pin numbering
A.2. Audio connectors
A.3. MMC/SD card socket pin numbering
A.4. MMC card
A.5. KMI connector
A.6. GPIO connector
A.7. Serial connector
A.8. SSP expansion interface
A.9. Smartcard contacts assignment
A.10. SCI expansion
A.11. Ethernet connector
A.12. USB interfaces
A.13. DVI connector
A.14. HDRX, HDRY HDRZ pin numbering
A.15. JTAG connector
A.16. USB debug connector
A.17. Integrated Logic Analyzer (ILA) connector
A.18. Trace Connector
B.1. Tile site multiplexed AXI timing
C.1. Signal groups on the PBX-A9 tile site
C.2. HDRX, HDRY, and HDRZ (upper) pin numbering

List of Tables

2.1. Boot Monitor startup behavior
2.2. STDIO redirection
2.3. Selecting the boot device
2.4. Cortex-A9 reset behavior
3.1. Serial interface device addresses
3.2. Reset signals
3.3. Interrupt allocations
4.1. System memory map
4.2. Memory map for standard peripherals
4.3. Boot memory
4.4. Memory chip selects and address range
4.5. Register map for status and system control registers
4.6. SYS_ID register bit assignments
4.7. SYS_OSCx register
4.8. SYS_OSCx register bit assignments
4.9. SYS_LOCK register bit assignments
4.10. Flag registers
4.11. SYS_RESETCTL register bit assignments
4.12. SYS_MCI register bit assignment
4.13. SYS_FLASH register bit assignments
4.14. SYS_CLCD register bit register assignments
4.15. SYS_MISC register bit assignment
4.16. SYS_DMAPSR register bit assignments
4.17. SYS_DMAPSR register bit coding
4.18. SYS_PEX_STAT register bit assignments
4.19. SYS_PCI_STAT register bit assignments
4.20. SYS_CTRL1 register bit assignments
4.21. SYS_CTRL2 register bit assignments
4.22. SYS_SERIAL_DATA register bit assignments
4.23. Daughterboard DDR2 memory remap
4.24. SYS_SERIAL_ADDR register bit assignments
4.25. SYS_PROCID0 register bit assignments
4.26. SYS_PROCID1 register bit assignments
4.27. SYS_TEST_OSCRESETx register
4.28. SYS_TEST_OSCx register
4.29. SYSCTRL implementation
4.30. SYS_CTRL0 register
4.31. SYS_CTRL1 register
4.32. AACI implementation
4.33. Modified AACI PeriphID3 register
4.34. CLCDC implementation
4.35. Values for different display resolutions
4.36. SMDMAC implementation
4.37. CoreSight APB memory map
4.38. DMC implementation
4.39. Typical DMC values for PL340 configuration registers
4.40. DDR2 DMC implementation
4.41. Ethernet implementation
4.42. GPIO implementation
4.43. GPIO2 and MCI status signals
4.44. Generic Interrupt Controller implementation
4.45. Interrupt control register addresses
4.46. CPU interface registers address offset values
4.47. CPU control register
4.48. Priority mask
4.49. Binary point
4.50. Binary Point bit values assignment
4.51. Interrupt acknowledge
4.52. End of interrupt
4.53. Running interrupt
4.54. Highest pending interrupt
4.55. Distribution registers address offset values
4.56. Distributor control
4.57. Controller type
4.58. Set-enable1
4.59. Reserved interrupts
4.60. Set-enable2
4.61. Reserved interrupts
4.62. Clear-enable1
4.63. Clear-enable2
4.64. Set-pending1
4.65. Set-pending2
4.66. Clear-pending1
4.67. Clear-pending2
4.68. Active1
4.69. Active2
4.70. Priority register address offsets and Interrupt IDs
4.71. CPU targets register address offsets and Interrupt IDs
4.72. Configuration register address offsets
4.73. Software interrupt
4.74. KMI implementation
4.75. MCI implementation
4.76. AXI to PCI bridge implementation
4.77. PCI bus memory map
4.78. RTC implementation
4.79. Serial bus implementation
4.80. Serial interface device addresses
4.81. SBCon 0 serial bus register
4.82. SBCon 1 serial bus register
4.83. SCI implementation
4.84. SSP implementation
4.85. SMC implementation
4.86. Timer implementation
4.87. UART implementation
4.88. USB implementation
4.89. USB controller base address
4.90. Watchdog implementation
4.91. CompactFlash implementation
4.92. CF_CTRL register bit assignments
A.1. CompactFlash connector pinout
A.2. Multimedia Card interface signals
A.3. Mouse and keyboard port signal descriptions
A.4. Serial plug signal assignment
A.5. SSP signal assignment
A.6. Smartcard connector signal assignment
A.7. Signals on SCI expansion connector
A.8. Ethernet signals
A.9. DVI connector signals
A.10. HDRX signals
A.11. HDRY signals
A.12. HDRZ signals
A.13. Trace Port A (TRACEA) connectors
A.14. Trace Port B (TRACEB) connector
B.1. Baseboard electrical characteristics
B.2. AC Specifications
D.1. STDIO redirection
D.2. Platform library options
D.3. NFU commands
D.4. NFU MANAGE commands
E.1. Standard Boot Monitor command set
E.2. Boot Monitor Configure commands
E.3. Boot Monitor Debug commands
E.4. Boot Monitor NOR flash commands

Proprietary Notice

Words and logos marked with © or ™ are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

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The system should be powered down when not in use.

The Platform Baseboard for A9 generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • ensure attached cables do not lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment and the receiver

  • connect the equipment into an outlet on a circuit different from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technician for help

Note

It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision A24 March 2009First release
Revision B23 May 2011Second release
Copyright © 2009-2011 ARM Limited. All rights reserved.ARM DUI 0440B
Non-ConfidentialID060911