2.3.1. CoreSight Serial Wire Debug

CoreSight Serial Wire Debug (SWD) replaces the 5-pin JTAG port with a clock and a single bi-directional data pin. It provides all the normal JTAG debug and test functionality plus real-time access to system memory without halting the core or requiring any target resident code. SWD uses an ARM standard bi-directional wire protocol, defined in the ARM Debug Interface v5 Architecture Specification (ARM IHI 0031) to pass data to and from the debugger and the target system in a highly efficient and standard way.

SWD is supported at the TRACE A connector on the CT-R4F. See Trace connectors for the connector pinout.

Note

SWD is not supported at the JTAG ICE connector J18 on the EB.

Copyright © 2009-2011 ARM Limited. All rights reserved.ARM DUI 0441C
Non-ConfidentialID021412