5.4.2. Timing parameters

The following timings are based on the grouped delays for the CT-R4F. They include the test chip input and output delay, and the delay because of the AXI bus multiplexing.

Table 5.8 shows the Global timing parameters.

Table 5.8. Global timing parameters

ParameterDescriptionMinMax
TclkCLK_POS_DN_OUT clock frequency33MHz40MHz
TisrstnSYSPOR de-asserted setup time before CLK_POS_DN_OUT5ns

Note

During reset the following interface requirements apply:

  • a master interface must drive ARVALID, AWVALID, and WVALID LOW

  • a slave interface must drive RVALID and BVALID LOW.

All other signals can be driven to any value.

A master interface must begin driving ARVALID, AWVALID, or WVALID HIGH only at a rising CLK_IN_MINUS1 edge after nSYSPORESET is HIGH.

The CT-R4F uses a multiplexed AXI bus. Figure 5.4 shows the CT-R4F multiplexed AXI bus input setup timing.

Figure 5.4. CT-R4F multiplexed AXI bus input setup timing

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Tctis

Input setup to clock

This is the longest time that the CT-R4F requires a valid AXI bus signal level to be presented at the Core Tile header before a rising or falling edge of CLK_POS_DN_OUT.

Figure 5.5 shows the CT-R4F multiplexed AXI bus output valid timing.

Figure 5.5. CT-R4F multiplexed AXI bus output valid timing

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Tctov

Core Tile output valid after clock

This is the longest delay between a rising or falling edge of CLK_POS_DN_OUT and a valid AXI bus output signal level arriving at the CT-R4F header.

Table 5.9 shows the CT-R4F AXI bus worst case timings when characterized for a slow process, a VDDCORE voltage of 0.95V, and a core temperature of 85°C.

Table 5.9. CT-R4F multiplexed AXI bus timing parameters

ParameterDescriptionMax
TctisInput setup time to either edge of CLK_POS_DN_OUT6ns
TctovOutput valid time from either edge of CLK_POS_DN_OUT5ns

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