2.1. Using the CT-R4F with an Emulation Baseboard

A typical ARM Cortex-R4F development system is shown in Figure 2.1.

To set up a development system using the Emulation Baseboard (EB):

  1. Fit the CT-R4F to tile site 1 on the EB.

  2. If required, fit a Logic Tile to tile site 2 on the EB.

  3. If required, fit additional Logic Tiles at either tile site to create a tile stack.

    Note

    The CT-R4F has no upper tile headers and can only be used either directly connected to the EB, or at the top of a tile stack. AXI bus multiplexing and demultiplexing logic must be included on any Logic Tile that connects directly to an AXI port on the EB or the CT-R4F. This might reduce the maximum operating frequency of the tile stack.

  4. If required, you can connect a RealView Analyzer Tile between the baseboard and a tile, to enable monitoring of signals using a logic analyzer. See Analyzer Tile User Guide (ARM DUI 0189) for details.

  5. You can also place an Interface Tile on top of the Logic Tile at tile site 2. The Logic Tile can be loaded with an appropriate image that contains your peripherals and the connectors on the Interface Tile can provide access to your peripherals. See Versatile/IT1 User Guide (ARM DUI 0188) for details.

  6. Connect a JTAG debugger to J18 on the baseboard (see Connecting a JTAG device to the EB).

  7. Set the CONFIG slide-switch S1 on the EB to ON.

  8. Supply power to the EB (see Supplying power to the EB).

  9. Load the appropriate FPGA images into the Logic Tiles. See the application note for details on the image to use and see the RealView Emulation Baseboard User Guide (Lead Free) (ARM DUI 0411) and the user guide for the Logic Tiles fitted for detailed programming procedures.

  10. Set the CONFIG slide-switch on the EB to OFF, power cycle the board, and load your application program.

    Note

    For details on how to load and run applications on an EB system, see the RealView Emulation Baseboard User Guide (Lead Free) (ARM DUI 0411).

Figure 2.1. Typical ARM Cortex-R4F processor development system

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