3.7.1. Multiplexing scheme

The AXI bus multiplexing and demultiplexing scheme is shown in Figure 3.8.

Figure 3.8. CT-R4F AXI bus multiplexing scheme

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Data is multiplexed as follows:

Dout is split bitwise into data Dout/A and Dout/B and is multiplexed onto Mux depending on the level of CLKin. When CLKin is HIGH, Dout/A is selected and when CLKin is LOW, Dout/B is selected. For example, when CLKin is HIGH, RDATA0[31:0] is selected and when CLKin is LOW, RDATA0[63:32] is selected. See HDRY signals for details of the AXI port 0 multiplexed signals, and HDRX signals for details of the AXI port 1 multiplexed signals.

Data is de-multiplexed as follows:

Dout/A is present on Mux when CLKin is HIGH and is latched onto DeMuxLatch when CLKin goes LOW. Dout/B is present on Mux when CLKin is LOW and is passed straight through as DeMux. DeMuxLatch and DeMux are combined bitwise as Din.

Note

This design requires that Dout is generated on the rising edge of CLKin, and that Din is captured on the rising edge of CLKin.

AXI signal routing

The CT-R4F AXI master port signals to the baseboard are 2:1 multiplexed onto pins X0 through to X143 on the HDRX header. Similarly, the CT-R4F AXI slave port signals from the baseboard are 2:1 multiplexed onto pins Y0 through to Y143 on the HDRY header.

See HDRX signals and HDRY signals for pinout information.

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