3.8.1. CT-R4F PLD signals

The CT-R4F PLD performs the following functions:

The CT-R4F PLD is controlled by the serial interface signals listed in Table 3.8. These signals connect to the EB via the HDRZ header.

Table 3.8. PLD control signals

SignalDirectionHDRZ busDescription
PLDCLKOutputZL230Clocks data into or out of the PLD.
PLDDINInputZL227Serial data input to PLD.
PLDDOUTOutputZL228Serial data output from PLD.
PLDnRSTInputZL229Resets the serial interface and signals the start of transfers.

The EB system FPGA implements registers that hold values sent to or received from the CT-R4F PLD using the 4-wire serial interface. The EB system FPGA and the CT-R4F PLD provide the serialization and deserialization logic required for the interface. The interface timing is shown in Figure 3.9.

Figure 3.9. 4-wire serial interface timing

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Data is output on the rising edge of PLDCLK and sampled on the falling edge. The interface is reset and re-synchronized by PLDnRST after each complete serial transfer. The rising edge of PLDnRST also indicates the start of a transfer. The data is transferred MSB first in both directions across the interface.

There are a total of 48 data bits (timeslots) in each bidirectional serial data stream:

The serial data stream PLDDOUT transmits data to the EB FPGA from the CT-R4F PLD Serial data read registers.

The serial data stream PLDDIN transmits data to the CT-R4F PLD Serial data write registers from the EB FPGA. Bits PLDDIN[47:46] are reserved and tied LOW.

The generic bit allocations for the serial streams are listed in Table 3.9.

Table 3.9. Serial streams bit allocations

BitSerial Bits PLDDINSerial Bits PLDDOUT
0DATA_DIRBOARD_ID[0]
1ADDR[12]BOARD_ID[1]
2ADDR[11]BOARD_ID[2]
3ADDR[10]BOARD_ID[3]
4ADDR[9]BOARD_ID[4]
5ADDR[8]BOARD_ID[5]
6ADDR[7]BOARD_ID[6]
7ADDR[6]BOARD_ID[7]
8ADDR[5]BOARD_ID[8]
9ADDR[4]BOARD_ID[9]
10ADDR[3]TC_PLL0_LOCK
11ADDR[2]TC_PLL1_LOCK
12ADDR[1]TC_PLL2_LOCK
13ADDR[0]ISP0_LOCKn
14DATA_IN[31]ISP1_LOCKn
15DATA_IN[30]ISP2_LOCKn
16DATA_IN[29]DATA_OUT[0]
17DATA_IN[28]DATA_OUT[1]
18DATA_IN[27]DATA_OUT[2]
19DATA_IN[26]DATA_OUT[3]
20DATA_IN[25]DATA_OUT[4]
21DATA_IN[24]DATA_OUT[5]
22DATA_IN[23]DATA_OUT[6]
23DATA_IN[22]DATA_OUT[7]
24DATA_IN[21]DATA_OUT[8]
25DATA_IN[20]DATA_OUT[9]
26DATA_IN[19]DATA_OUT[10]
27DATA_IN[18]DATA_OUT[11]
28DATA_IN[17]DATA_OUT[12]
29DATA_IN[16]DATA_OUT[13]
30DATA_IN[15]DATA_OUT[14]
31DATA_IN[14]DATA_OUT[15]
32DATA_IN[13]DATA_OUT[16]
33DATA_IN[12]DATA_OUT[17]
34DATA_IN[11]DATA_OUT[18]
35DATA_IN[10]DATA_OUT[19]
36DATA_IN[9]DATA_OUT[20]
37DATA_IN[8]DATA_OUT[21]
38DATA_IN[7]DATA_OUT[22]
39DATA_IN[6]DATA_OUT[23]
40DATA_IN[5]DATA_OUT[24]
41DATA_IN[4]DATA_OUT[25]
42DATA_IN[3]DATA_OUT[26]
43DATA_IN[2]DATA_OUT[27]
44DATA_IN[1]DATA_OUT[28]
45DATA_IN[0]DATA_OUT[29]
46Not usedDATA_OUT[30]
47Not usedDATA_OUT[31]

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