3.4.1. Resets

Several resets are required by the baseboard and the CT-R4F.

This section describes the resets and contains the following subsections:

Baseboard resets

The reset logic on the baseboard is required to initialize the baseboard and attached Logic Tiles and Core Tiles. The baseboard has several reset sources and generates several reset signals.

The EB reset sources and the function of the EB reset signals are described in detail in the RealView Emulation Baseboard User Guide (Lead Free) (ARM DUI 0411).

CT-R4F resets

The CT-R4F requires the following reset signals at the HDRZ header:

Table 3.4. CT-R4F Resets

NameDescription
nSYSPOR

Power-on reset from the baseboard. This reset is released approximately 7μs after the global signal GLOBAL_DONE goes HIGH indicating that all programmable devices in the system have been configured.

nCOLDRST

Cold reset from the baseboard. This signal is connected to nSYSPOR in the EB FPGA.

nSYSRST

Main reset from the baseboard. This reset is released approximately 20μs after nSYSPOR goes HIGH or goes LOW after nSRST goes LOW and returns HIGH approximately 20μs after nSRST goes HIGH.

nWARMRST

This is the warm reset from the baseboard. This signal is connected to nSYSRST in the EB FPGA.

D_nSRSTnSYSRST request from the debug system.
C_nSRSTnSYSRST request from the config system.
D_nTRST

JTAG reset to the debug JTAG scan chain.

C_nTRST

JTAG reset to the config JTAG scan chain.

PLDnRSTResets and restarts the 4-wire serial data transfer to the CT-R4F PLD.

ARM Cortex-R4F test chip resets

Figure 3.4 shows how the resets to the ARM Cortex-R4F test chip are controlled by the CT-R4F PLD.

Figure 3.4. CT-R4F test chip reset control

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The ARM Cortex-R4F test chip resets are listed in Table 3.5.

Table 3.5. CT-R4F test chip resets

NameFunctionDescription
nSYSPOR_RESET_IOWarm resetActive low reset for the CP14 debug logic.
nSOC_RESET_IOSOC resetActive low reset for the AXI sub-system in the test chip.
nDBG_RESET_IODebug resetActive low reset for the APB logic, CoreSight ETM, and CoreSight DAP but excludes the CP14 debug logic.
nRESET_IOProcessor ResetActive low reset for the ARM Cortex-R4F processor.
nPLLRSTPLL resetActive low reset for all the test chip PLLs.
nCFGRSTConfig Block resetActive low Reset for the Configuration Block in the test chip.

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