4.3.1. CT_R4F_CTRL register

The CT_R4F_CTRL register is at serial stream address 0x100A. Figure 4.9 shows the bit allocations within the register.

Figure 4.9. CT_RF_CTRL register

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The function of the register bits are listed in Table 4.20.

Table 4.20. CT_R4F_CTRL register bit assignments

BitsAccessNameResetDescription
[31:25]Read onlyb0000000Reserved
[24]Read onlyDMACIRQABORTbXSet HIGH by the ARM Cortex-R4F test chip DMAC when an abort occurs.
[23:17]Read onlyb0000000Reserved
[16]Read onlyCLPOWERbxStatus of CLCD Power Enable.
[15:12]Read onlyb0000Reserved
[11]Read/WriteRESET_CTRL[3]b0Enables nWARMRST from the baseboard to control nSOC_RESET_IO to the ARM Cortex-R4F test chip.
[10]Read/WriteRESET_CTRL[2]b0Enables nWARMRST from the baseboard to control nDBG_RESET_IO to the ARM Cortex-R4F test chip.
[9]Read/WriteRESET_CTRL[1]b0Set to b0 for normal operation.
[8]Read/WriteRESET_CTRL[0]b0Enables nWARMRST from the baseboard to control nRESET_IO to the ARM Cortex-R4F test chip.
[7:1]Read onlyb0000000Reserved
[0]Read/WriteJTAG_SRCb0When nCFGEN is LOW, selects the JTAG source as the HDRZ header or the Trace A connector: b0 = JTAG source is at the HDRZ header. b1 = JTAG source is at the TRACE A connector.

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