3.4.3. Interrupts

A simplified diagram of the interrupt routing in the ARM Cortex-R4F test chip is shown in Figure 3.6.

Figure 3.6. ARM Cortex-R4F interrupt routing

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The PL192 VIC in the test chip can be bypassed and the IRQ and FIQ inputs to the ARM Cortex-R4F processor sourced externally. When used with the EB, the external IRQ and FIQ are sourced respectively by Generic Interrupt Controllers, GIC1 and GIC2 in the EB FPGA. See RealView Emulation Baseboard User Guide (Lead Free) (ARM DUI 0411) for further information.

Note

The source of the IRQ and FIQ interrupts is set during reset by the configuration register CT_R4F_TC_CFG2. See CT_R4F_TC_CFG2 register for details. By default, the VIC in the test chip is not bypassed on the CT-R4F.

See ARM PrimeCell Vectored Interrupt Controller (PL192) Technical Reference Manual (ARM DDI 0273) for details on the PL192 VIC in the test chip.

Table 3.6 lists the ARM Cortex-R4F VIC interrupt allocations.

Note

The twelve internal peripheral interrupts R4F_TC_INT[11:0], from the ARM Cortex-R4F test chip, are made available at the HDRZ header. See Table 3.6 for the interrupt Z bus allocations. This enables the internal PL192 VIC to be bypassed and an external interrupt controller to be used independently. With the PL192 VIC bypassed, interrupt inputs VICINITSOURCE[0] and VICINITSOURCE[1] to the CT-R4F must provide the external nFIQ and nIRQ signals respectively to the ARM Cortex-R4F processor.

Table 3.6. ARM Cortex-R4F test chip VIC interrupt allocations

VIC Interrupt NumberInterrupt NameSourceZ Bus signalDescription
0(reserved)Test chipZ210Do not connect, reserved for production test.
1(reserved)Test chipZ211Do not connect, reserved for production test.
2DMAC_IRQ[0]PL330 DMACZ213Active HIGH interrupt outputs. The DMAC sets irq<N> HIGH when it executes a DMASEV instruction for event N, if the Interrupt Enable Register is programmed to signal an interrupt for event N.
3DMAC_IRQ[1]Z214
4DMAC_IRQ[2]Z215
5DMAC_IRQ[3]Z219
6DMAC_IRQ_ABORTPL330 DMACThe DMAC sets this signal HIGH when an abort occurs and it remains HIGH if any thread is in the Faulting completing state or Faulting state. If all threads are not in the Faulting completing state or Faulting state then the DMAC sets this signal LOW.
7CLCDINTRPL111 CLCDCZ212Active HIGH single combined interrupt for the CLCDC.
8(reserved)Test chip
9FPDZCARM Cortex-R4F FPUMasked floating-point divide-by-zero exception.
10FPIDCMasked floating-point input denormal exception.
11FPIOCMasked floating-point invalid operation exception.
12FPIXCMasked floating-point inexact exception.
13FPOFCMasked floating-point overflow exception.
14FPUFCMasked floating-point underflow exception.
15nPMUIRQARM Cortex-R4FInterrupt request by Performance Monitor Unit (PMU).
16nVALFIQARM Cortex-R4FRequest for an Interrupt from the ARM Cortex-R4F system validation register.
17nVALIRQARM Cortex-R4FRequest for a Fast Interrupt from the ARM Cortex-R4F system validation register.
18TIMINT1SP804 TimerZ220Timer1 interrupt, active HIGH.
19TIMINT2Z221Timer2 interrupt, active HIGH.
20TIMINTCZ222Combined timer interrupt, active HIGH.
21CTIRQETM-R4/CTIETM Cross Trigger interrupt, active HIGH, connects to inverted ETM CTI output CTITRIGOUT[3].
22COMMRXARM Cortex-R4FZ217Write-DTR full. Write Data Transfer Register (DTR) full from ARM Cortex-R4F processor debug system.
23COMMTXZ218Read-DTR empty. Read Data Transfer Register (DTR) empty from ARM Cortex-R4F processor debug system.
24VICINTSOURCE_IN[0]HDRZ headerZ200External interrupt 0, is the FIQ from the EB GIC. It connects to VICINTSOURCE[24] on the PL192 VIC. If the VIC is bypassed, it connects also to the FIQ input of the ARM Cortex-R4F processor.
25VICINTSOURCE_IN[1]HDRZ headerZ201External interrupt 1, is the IRQ from the EB GIC. It connects to VICINTSOURCE[25] on the PL192 VIC. If the VIC is bypassed, it connects also to the IRQ input of the ARM Cortex-R4F processor.
26VICINTSOURCE_IN[2]HDRZ headerZ202External interrupt 2, is a general purpose peripheral interrupt. It connects to VICINTSOURCE[26] on the PL192 VIC.
27VICINTSOURCE_IN[3]HDRZ headerZ203External interrupt 3, is a general purpose peripheral interrupt. It connects to VICINTSOURCE[27] on the PL192 VIC.
28VICINTSOURCE_IN[4]HDRZ headerZ204General purpose external interrupt. It connects to VICINTSOURCE[28] on the PL192 VIC.
29VICINTSOURCE_IN[5]HDRZ headerZ205General purpose external interrupt. It connects to VICINTSOURCE[29] on the PL192 VIC.
30VICINTSOURCE_IN[6]HDRZ headerZ206General purpose external interrupt. It connects to VICINTSOURCE[30] on the PL192 VIC.
31VICINTSOURCE_IN[7]nVALRESET (default) or HDRZ headerZ207Connects to VICINTSOURCE[31] on the PL192 VIC. If CT_R4F_TC_CF2[27] is set to bypass the PL192 VIC, the interrupt source is nVALRESET, a request for a reset from the ARM Cortex-R4F system validation register. If the PL192 VIC is not bypassed, it is a general purpose external interrupt from the HDRZ header.
CT_nFIQ_EXTPL192 VICZ208nFIQ interrupt from the PL192 VIC in the ARM Cortex-R4F test chip.
CT_nIRQ_EXTPL192 VICZ209nIRQ interrupt from the PL192 VIC in the ARM Cortex-R4F test chip.

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