4.2.2. ARM Cortex-R4F test chip configuration after reset

The CT_R4F_TC_CFG0 register can only be accessed at reset using the 4-wire serial interface. Some of the bit fields in the CT_R4F_TC_CFG1 and CT_R4F_TC_CFG2 registers can be accessed after reset using the APB port of the SCC.

The base address of the SCC APB port is set by the value of REMAP, which is read from the CT_R4F_TC_CFG2[31:29] register field during reset. See Table 4.13 for details.

The SCC registers APB port addresses for all REMAP options are listed in Table 4.14.

Table 4.14. SCC APB port addresses

SCC registerREMAP = 000REMAP = 001REMAP = 010REMAP = 100
CT_R4F_TC_CFG10xE00070040xD00070040xE00070040xD0007004
CT_R4F_TC_CFG20xE00070080xD00070080xE00070080xD0007008

CT_R4F_TC_CFG1 register

The CT_R4F_TC_CFG1 register is at offset 0x0004. Figure 4.5 shows the SCC APB port accessible fields within the register.

Figure 4.5. CT_R4F_TC_CFG1 register

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The function of the register bits are listed in Table 4.15.

Table 4.15. CT_R4F_TC_CFG1 register bit assignments

BitsAccessNameResetDescription
[31]Read/WriteCTINIDENb1Non-Invasive Debug Enable (CTI)
[30]Read/WriteDBGENb1Non-Invasive Debug Enable (CPU)
[29:26]Read/WriteCFGBTCMSZb0111Soft BTCM size config (maximum BTCM size is 64K). Valid values are: 0000 = 0KB 0011 = 4KB 0100 = 8KB 0101 = 16KB 0110 = 32KB 0111 = 64KB
[25:22]Read/WriteCFGATCMSZb0111Soft ATCM size config (maximum ATCM size is 64K). Valid values are: 0000 = 0KB 0011 = 4KB 0100 = 8KB 0101 = 16KB 0110 = 32KB 0111 = 64KB
[21]Read/WriteEDBGRQb0 
[20]Read/WriteDBGNOCLKSTOPb0The ARM Cortex-R4F processor does not stop the clocks when entering WFI state
[19]Read/WriteCFGNMFIb0 
[18:16]Write ignored, read undefinedUndefined
[15]Read/WriteNIDENb1Non-Invasive Debug Enable (CPU)
[14:12]Write ignored, read undefinedUndefined
[11]Read/WriteETMNIDENb1Non-Invasive Debug Enable (ETM)
[10]Read/WriteETMDBGENb1Invasive Debug Enable (ETM)
[9:0]Write ignored, read undefinedUndefined

CT_R4F_TC_CFG2 register

The CT_R4F_TC_CFG2 register is at offset 0x0008. Figure 4.6 shows the SCC APB port accessible fields within the register.

Figure 4.6. CT_R4F_TC_CFG2 register

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The function of the register bits are listed in Table 4.16.

Table 4.16. CT_R4F_TC_CFG1 register bit assignments

BitsAccessNameResetDescription
[31:4]Write ignored, Read as zero0x0000000Undefined
[3:1]Write ignored, Read as zerob000Undefined
[0]Read/WriteCTIDBGENb1Invasive Debug Enable (CTI)

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