4.1.1. Peripheral memory maps

The peripheral memory maps for the four remap options are listed in Table 4.1 and Table 4.2. Not all configuration options for the ARM Cortex-R4F processor can be set using the Serial Configuration Controller (SCC) APB port listed in Table 4.1 and Table 4.2, some can only be set from the SCC serial configuration port during system reset.

Table 4.1. Peripheral memory map (REMAP = 000 or 010)

PeripheralAddress range (REMAP = 000 or 010)Bus typeRegion size
Reserved0xE0000000-0xE0003FFFAPB16KB
Dynamic Memory Controller (PL340)0xE0004000-0xE0004FFFAPB4KB
Direct Memory Access Controller (PL330)0xE0005000-0xE0005FFFAPB4KB
High-Performance Matrix (PL301)0xE0006000-0xE0006FFFAPB4KB
Serial Configuration Controller (SCC)0xE0007000-0xE0007FFFAPB4KB
Reserved0xE0008000-0xE0008FFFAPB4KB
Timer (SP804)0xE0009000-0xE0009FFFAPB4KB
Color LCD Controller (PL111)0xE000A000-0xE000AFFFAHB4KB
Reserved (PL111 aliased)0xE000B000-0xE000DFFFAHB12KB
Vectored Interrupt Controller (PL192)0xE000E000-0xE000EFFFAHB4KB
Reserved (PL192 aliased)0xE000F000-0xE0011FFFAHB12KB

Table 4.2. Peripheral memory map (REMAP = 001 or 100)

PeripheralAddress range (REMAP = 001 or 100)Bus typeRegion size
Reserved0xD0000000-0xD0003FFFAPB16KB
Dynamic Memory Controller (PL340)0xD0004000-0xD0004FFFAPB4KB
Direct Memory Access Controller (PL330)0xD0005000-0xD0005FFFAPB4KB
High-Performance Matrix (PL301)0xD0006000-0xD0006FFFAPB4KB
Serial Configuration Controller (SCC)0xD0007000-0xD0007FFFAPB4KB
Reserved0xD0008000-0xD0008FFFAPB4KB
Timer0xD0009000-0xD0009FFFAPB4KB
Color LCD Controller (PL111)0xD000A000-0xD000AFFFAHB4KB
Reserved (PL111 aliased)0xD000B000-0xD000DFFFAHB12KB
Vectored Interrupt Controller (PL192)0xD000E000-0xD000EFFFAHB4KB
Reserved (PL192 aliased)0xD000F000-0xD0011FFFAHB12KB

Dynamic Memory Controller (DMC)

The PL340 PrimeCell Dynamic Memory Controller (DMC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.

The DMC implementation controls 512MB of 64-bit wide SDRAM organized as two banks.

Table 4.3. DMC implementation

PropertyValue
Location ARM Cortex-R4F test chip
Memory base address
  • REMAP = 000 or 010: 0xE0004000

  • REMAP = 001 or 100: 0xD0004000

Interrupt
DMA
Release versionARM DMC PL340 r1p0
Reference documentationPrimeCell Dynamic Memory Controller (PL340) Technical Reference Manual DDI 0331.

The DMC controls 2 banks of 512MB SDRAM memory on the CT-R4F. Sample programs that configure and use dynamic memory can be found on the CD that accompanies the Core Tile.

Direct Memory Access Controller (DMAC)

The PL330 PrimeCell Direct Memory Access Controller (DMAC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.

The DMAC can access the local SDRAM, test chip AXI RAM, the ARM Cortex-R4F processor slave port, and the CT-R4F slave port. The PL330 is configured to support 4 banks of SDRAM with a memory bus width of 64-bit. The peripheral request interface is not implemented.

Table 4.4. DMAC implementation

PropertyValue
Location ARM Cortex-R4F test chip
Memory base address
  • REMAP = 000 or 010: 0xE0005000

  • REMAP = 001 or 100: 0xD0005000

Interrupt
VICINTSOURCE[2]

TC_DMAC_IRQ0

VICINTSOURCE[3]

TC_DMAC_IRQ1

VICINTSOURCE[4]

TC_DMAC_IRQ2

VICINTSOURCE[5]

TC_DMAC_IRQ3

VICINTSOURCE[6]

TC_DMAC_IRQ_ABORT

Release versionARM DMAC PL330 r0p0
Reference documentationPrimeCell DMA Controller (PL330) Technical Reference Manual DDI 0424.

High Performance Matrix (HPM)

The PL301 PrimeCell High Performance Matrix (HPM) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.

The HPM is a highly configurable auto-generated AMBA 3 bus subsystem, based around a high-performance AXI cross-bar switch known as the AXI bus matrix, and extended by AMBA infrastructure components.

Table 4.5. DMAC implementation

PropertyValue
Location ARM Cortex-R4F test chip
Memory base address
  • REMAP = 000 or 010: 0xE0006000

  • REMAP = 001 or 100: 0xD0006000

Interrupt
Release versionARM HPM PL301 r1p0
Reference documentationPrimeCell High-Performance Matrix (PL301) Technical Reference Manual DDI 0397.

Serial Configuration Controller (SCC)

The Serial Configuration Controller (SCC) is a custom AMBA compliant SoC peripheral.

During reset, the ARM Cortex-R4F test chip is configured by the CT-R4F PLD via the SCC serial configuration port. After reset, there is limited access to the SCC internal configuration registers at the SCC APB port.

Table 4.6. SCC implementation

PropertyValue
Location ARM Cortex-R4F test chip
Memory base address
  • REMAP = 000 or 010: 0xE0007000

  • REMAP = 001 or 100: 0xD0007000

Interrupt
Release versionARM Custom IP
Reference documentationSee CT-R4F configuration for configuration register details.

Timer

The SP804 Dual-Timer Module is an AMBA compliant SoC peripheral that is developed and tested by ARM Limited.

The Dual-Timer Module consists of two programmable 32/16-bit down counters that can generate interrupts on reaching zero.

Table 4.7. Timer implementation

PropertyValue
Location ARM Cortex-R4F test chip
Memory base address
  • REMAP = 000 or 010: 0xE0009000

  • REMAP = 001 or 100: 0xD0009000

Interrupt
VICINTSOURCE[18]

TC_TIMINT1

VICINTSOURCE[19]

TC_TIMINT2

VICINTSOURCE[20]

TC_TIMINTC

Release versionARM Dual-Timer SP804 r1p2
Reference documentationARM Timer Module (SP804) Technical Reference Manual ARM DDI 0271

Color LCD Controller (CLCDC)

The PL111 PrimeCell Color LCD Controller (CLCDC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.

The CLCDC master can access the local SDRAM, test chip AXI RAM, and the CT-R4F slave port.

Table 4.8. CLCDC implementation

PropertyValue
Location ARM Cortex-R4F test chip
Memory base address
  • REMAP = 000 or 010: 0xE000A000

  • REMAP = 001 or 100: 0xD000A000

Interrupt
VICINTSOURCE[7]

CLCDINTR

Release versionARM CLCDC PL111 (version r0p0)
Reference documentationARM PrimeCell Color LCD Controller (PL111) Technical Reference Manual DDI 0293.

Vectored Interrupt Controller (VIC)

The PL192 PrimeCell Vectored Interrupt Controller (VIC) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.

Table 4.9. CLCDC implementation

PropertyValue
Location ARM Cortex-R4F test chip
Memory base address
  • REMAP = 000 or 010: 0xE000E000

  • REMAP = 001 or 100: 0xD000E000

Interrupt
VICINTSOURCE[7]

CLCDINTR

Release versionARM CLCDC PL111 (version r0p0)
Reference documentationARM PrimeCell Color LCD Controller (PL111) Technical Reference Manual DDI 0293.

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