4.2.1. ARM Cortex-R4F test chip configuration at reset

Because of the limited pin count and extensibility of the ARM Cortex-R4F test-chip design, all static configuration inputs are programmed serially. During reset, the CT-R4F PLD configures the ARM Cortex-R4F test chip by transferring data from the CT_R4F_TC_CFG[0:2] registers in the CT-R4F PLD using the serial interface port of the Serial Configuration Controller (SCC) in the test chip.

The default values are supplied by the EB via the 4-wire serial interface during reset.

Note

Some configuration data can be changed using the APB port of the SCC after reset. See ARM Cortex-R4F test chip configuration after reset for details.

The CT_R4F_TC_CFG0 register configuration signals that are sent serially during reset are listed in Table 4.11. The CT_R4F_TC_CFG0 register address is: 0x0000.

Table 4.11. CT_R4F_TC_CFG0 configuration signals

Config word bitConfig signal nameARM Cortex-R4F test chip signal nameDefault valueDescription
[3:0]CONFIG[3:0]M_PLL0b0101ARM Cortex-R4F test chip PLL0 setup
[6:4]CONFIG[6:4]N_PLL0b001
[7]CONFIG[7]BYPASS_PLL0b0
[8]CONFIG[8]ENABLE_PLL0b1
[9]CONFIG[9]DESKEW_PLL0b0
[10]CONFIG[10]RANGE_PLL0b1
[11]CONFIG[11]MACRO_BYPASS_PLL0b0
[15:12]CONFIG[15:12]M_PLL1b0001ARM Cortex-R4F test chip PLL1 setup PLL1 is bypassed by default
[18:16]CONFIG[18:16]N_PLL1b001
[19]CONFIG[19]BYPASS_PLL1b1
[20]CONFIG[20]ENABLE_PLL1b0
[21]CONFIG[21]DESKEW_PLL1b1
[22]CONFIG[22]RANGE_PLL1b0
[23]CONFIG[23]MACRO_BYPASS_PLL1b0
[27:24]CONFIG[27:24]M_PLL2b0001ARM Cortex-R4F test chip PLL2 setup
[30:28]CONFIG[30:28]N_PLL2b001
[31]CONFIG[31]BYPASS_PLL2b0

The CT_R4F_TC_CFG1 register configuration signals that are sent serially during reset are listed in Table 4.12. The CT_R4F_TC_CFG1 register address is: 0x0004.

Table 4.12. CT_R4F_TC_CFG1 configuration signals

Config word bitConfig signal nameARM Cortex-R4F test chip signal nameDefault valueDescription
[0]CONFIG[32]ENABLE_PLL2b1ARM Cortex-R4F test chip PLL2 setup
[1]CONFIG[33]DESKEW_PLL2b1
[2]CONFIG[34]RANGE_PLL2b0
[3]CONFIG[35]MACRO_BYPASS_PLL2b0
[5:4]CONFIG[37:36]CLOCK_MODEb01CPU_CLK:ACLK:PCLK frequency ratio: 00 = 8:8:1 01 = 16:8:1 10 = 16:4:1 11 = 16:2:1
[6]CONFIG[38]CFGEEb0 
[7]CONFIG[39]CFGIEb0 
[8]CONFIG[40]CPUHALTnb1 
[9]CONFIG[41]ENTCM1Fb1 
[10]CONFIG[42]ETMDBGENb1Invasive Debug Enable (ETM)
[11]CONFIG[43]ETMNIDENb1Non-Invasive Debug Enable (ETM)
[12]CONFIG[44]INITRAMAb0Enable ATCM boot
[13]CONFIG[45]INITRAMBb0Enable BTCM boot
[14]CONFIG[46]LOCZRAMAb1 
[15]CONFIG[47]NIDENb1Non-Invasive Debug Enable (CPU)
[16]CONFIG[48]SLBTCMSBb0 
[17]CONFIG[49]TEINITb0 
[18]CONFIG[50]VINITHIb0 
[19]CONFIG[51]CFGNMFIb0 
[20]CONFIG[52]DBGNOCLKSTOPb0The processor does not stop the clockswhen entering WFI state
[21]CONFIG[53]EDBGRQb1A request to theARM Cortex-R4F processor to enter the debug state.
[25:22]CONFIG[57:54]CFGATCMSZb0111Soft ATCM size config (maximum ATCM size is 64K). Valid values are: 0000 = 0KB 0011 = 4KB 0100 = 8KB 0101 = 16KB 0110 = 32KB 0111 = 64KB
[29:26]CONFIG[61:58]CFGBTCMSZb0111Soft BTCM size config (maximum BTCM size is 64K). Valid values are: 0000 = 0KB 0011 = 4KB 0100 = 8KB 0101 = 16KB 0110 = 32KB 0111 = 64KB
[30]CONFIG[62]DBGENb1Non-Invasive Debug Enable (CPU)
[31]CONFIG[63]CTINIDENb1Non-Invasive Debug Enable (CTI)

The CT_R4F_TC_CFG2 register configuration signals that are sent serially during reset are listed in Table 4.13. The CT_R4F_TC_CFG2 register address is: 0x0008.

Table 4.13. CT_R4F_TC_CFG2 configuration signals

Config word bitConfig signal nameARM Cortex-R4F test chip signal nameDefault valueDescription
[0]CONFIG[64]CTIDBGENb1Invasive Debug Enable (CTI)
[1]CONFIG[65]Reservedb0
[26:2]CONFIG[90:66]Reserved0x000000
[27]CONFIG[91]CPU_nFIQEXT_SELb0Source for CPU_nFIQEXT for VIC bypass.
[28]CONFIG[92]CPU_nIRQEXT_SELb0Source for CPU_nIRQEXT for VIC bypass.
[29]CONFIG[93]REMAP_0b0Memory REMAP selection See Memory maps for details.
[30]CONFIG[94]REMAP_1b0
[31]CONFIG[95]REMAP_2b0

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