4.2. CT-R4F configuration

To maintain compatibility with other board products, the standard 4-wire serial interface implemented on ARM baseboards sends and receives data to and from registers in the CT-R4F PLD. See Overview of Core Tile configuration for details of the 4-wire serial interface implementation and the format of the address and data stream. The CT-R4F PLD registers and the serial stream addresses are listed in Table 4.10.

Table 4.10. CT-R4F PLD registers

0x0000CT_R4F_TC_CFG0WriteCT-R4F test chip config word 0. See ARM Cortex-R4F test chip configuration at reset for details.
0x0004CT_R4F_TC_CFG1WriteCT-R4F test chip config word 1.
0x0008CT_R4F_TC_CFG2WriteCT-R4F test chip config word 2.
0x1000CT_R4F_PLD_IDReadCT-R4F PLD ID. See CT-R4F ID register for details.
0x1004CT_R4F_OSC0WriteCT-R4F test chip CPU_CLK PLL reference clock.
0x1005CT_R4F_OSC1WriteCT-R4F test chip MCLK PLL reference clock.
0x1006CT_R4F_OSC2WriteCT-R4F test chip CLCD reference clock.
0x1008CT_R4F_DVIWriteCT-R4F DVI and CLCD control. See CT_RF_DVI register for details.
0x100ACT_R4F_CTRLRead/WriteCT-R4F control. See CT_R4F_CTRL register for details.
0x1010CT_R4F_CTRL_ADC0ReadCT-R4F ADC channel 0 − ARM Cortex-R4F processor current. See CT_R4F_ADC registers for details.
0x1011CT_R4F_CTRL_ADC1ReadCT-R4F ADC channel 1 − Reserved.
0x1012CT_R4F_CTRL_ADC2ReadCT-R4F ADC channel 2 − test chip sub-system current.
0x1013CT_R4F_CTRL_ADC3ReadCT-R4F ADC channel 3 − ARM Cortex-R4F processor and test chip sub-system supply voltage.
0x1014CT_R4F_CTRL_ADC4ReadCT-R4F ADC channel 4 − test chip PLLs supply voltage.
0x1015CT_R4F_CTRL_ADC5ReadCT-R4F ADC channel 5 − test chip I/O supply voltage.
0x1016CT_R4F_CTRL_ADC6ReadCT-R4F ADC channel 6 − Reserved.
0x1017CT_R4F_CTRL_ADC7ReadCT-R4F ADC channel 7 − Reserved.

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