4.2.4. DVI and CLCD configuration

To maximize the performance of the CLCD interface, the CT-R4F includes a local triple video DAC, DVI transmitter, and DVI interface connector to provide direct support for both digital and analog displays. The CLCD panel side signals can also be routed to a baseboard CLCD interface through the HDRZ header. A simplified diagram of the CLCD signal routing is shown in Figure 3.7. The routing of the CLCD signals is controlled by the baseboard using the 4-wire interface to the CT_R4F_DVI register in the CT-R4F PLD.

CT_RF_DVI register

The CT_R4F_DVI register is at serial stream address 0x1008. Figure 4.8 shows the bit allocations within the register.

Figure 4.8. CT_R4F_DVI register

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The function of the register bits are listed in Table 4.19.

Table 4.19. CT_R4F_DVI register bit assignments

[31]Read onlyCLPOWERb0CLCD power enable
[3:1]Read/WriteDVI_CTRLb000Set to b000 for normal operation
[0]Read/WriteBBDVI_nENb0Enables the CT-R4F CLCD controller panel side outputs to the HDRZ header bus ZL[0:31]. See DVI and CLCD routing and HDRZ signals for further details.

Copyright © 2009-2011 ARM Limited. All rights reserved.ARM DUI 0441C