2.4. Using the CT-R4F with a custom baseboard

If you are designing a custom baseboard to accept a CT-R4F, you must ensure that your board meets the following requirements:

Mechanical layout

Mechanical layout details are available from ARM, contact ARM Support for further information.

Power supplies

The CT-R4F uses 5V and 3V3 supplies connected through power-blades in the header connectors. See Header connectors for details. The CT-R4F uses the 5V supply to:

  • generate the 1V2 supply for the ARM Cortex-R4F test chip core and 2V6 supply for the ARM Cortex-R4F test chip I/O

  • generate the 2V5 supply for the ARM Cortex-R4F test chip PLL

  • generate the 1V8 supply for the PLD core.

The 3V3 supply is used by the PLD I/O, SDRAM and all external CT-R4F interfaces.

The test chip and PLL voltages and currents are monitored by an Analog to Digital Converter (ADC) on the CT-R4F and the values are transmitted to the baseboard using the 4-wire serial link in the PLD. See Power supply monitoring for details on the voltage and current monitoring scheme.

Clock control

Your primary reference clock must be supplied by an attached Logic Tile or baseboard. The CT-R4F clocking system is described in Chapter 3 CT-R4F Hardware Description and the ARM Cortex-R4F test chip specific clocking requirements are described in Chapter 4 Programmer’s Reference. See also the ARM Cortex-R4 and Cortex-R4F Technical Reference Manual (ARM DDI 0363) for further information on the AXI interface clocking requirements. For an example of the clock structure design, see Application Note 217 supplied with the product on the Versatile CD.

JTAG control

The CT-R4F provides a JTAG port at the TRACE A connector. The baseboard may also provide a JTAG connector and route the JTAG signals to the HDRZ header on the CT-R4F. JTAG routing is described in JTAG support.

AXI bus multiplexing

A multiplexing scheme is necessary to reduce the number of pins required on the HDRX and HDRY headers. Bus multiplexing is managed by the ARM Cortex-R4F test chip. A compatible multiplexing scheme must be implemented by the custom baseboard. See AXI bus multiplexing for details of the multiplexing requirements.

AXI slaves

In order for the ARM Cortex-R4F to boot, the baseboard must implement AXI slaves that cover the 4GB memory map.

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