1.2. About Core Tiles

Core Tiles are development boards that enable you to develop products based on ARM processors and AMBA® interfaces. Core Tiles are built around test chips, which are ASIC implementations of one or more ARM processors. Core Tiles provide one or more AMBA interfaces from the processor so that it can be connected to an AMBA-based system. See the AMBA Specification (Rev 2.0) (ARM IHI 0011) and the AMBA AXI™ Protocol Specification (ARM IHI 0022) for further information.

The Core Tile must be used in conjunction with a baseboard that implements the necessary system and memory controllers. For example, the CT-R4F when combined with the RealView® Emulation Baseboard (EB) provides a standalone system for ARM Cortex-R4F product development. Third-party or custom baseboards can also be used.


The CT-R4F, like other Core Tiles, is only fully supported by ARM when used in combination with an EB, if a third-party or custom baseboard is used, ARM can provide limited support. Use of Core Tiles with a Platform Baseboard (PB) is not supported.

Core Tiles do not have power connectors. The tiles must be stacked on a baseboard that provides a power connection. The Core Tiles also require a reference clock (or clocks) to be supplied by the attached baseboard.


Most Core Tiles require the EB or custom baseboard to provide the JTAG port connector. The CT-R4F also provides the JTAG port at the TRACE A connector. The JTAG port to be used is determined at reset.

Through-board connectors on most tile products enable stacking of multiple tiles. Multiple combinations of Core Tile and Logic Tile can be used to create a multiprocessor system.


The CT-R4F does not include upper board connectors and therefore can only be used at the top of a tile stack.

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