2.3. Connecting JTAG debugging equipment

The CT-R4F provides a JTAG port at the HDRZ header for use with an Evaluation Baseboard (EB) or custom baseboard that provides a JTAG ICE connector. A JTAG port is also provided at the TRACE A connector for use with RealView ICE. CoreSight Serial Wire Debug (SWD) is also supported at the TRACE A connector.

During configuration the JTAG source is determined by the JTAG_SRC field in the CT_R4F_CTRL register or by the configuration switch (S1-1) on the CT-R4F. For further information on determining the JTAG source see CT_R4F_CTRL register and Configuration switches.

External JTAG equipment can be used to:

Selection between debugging programs and downloading new images to the FPGA is controlled by the CONFIG slide-switch S1 on the EB. See the documentation supplied with the EB for more details on connecting JTAG and using the CONFIG slide-switch.


Because the CT-R4F does not provide nonvolatile memory, programs are lost if the power is removed. Use EB flash memory for nonvolatile storage.

The flash memory can be:

  • any unused space in the EB NOR flash

  • nonvolatile memory available in the EB PISMO memory expansion slots J35.

Do not use spare EB configuration flash space (address range: 0x4C000000-0x4DFFFFFF) for program storage.

See the Programmer’s Reference chapter in the RealView Emulation Baseboard User Guide (Lead Free) (ARM DUI 0411) for details of the EB memory map.

The JTAG ICE connector J18 provides a set of signals that enable debugging equipment to be used. When debugging a development system with multiple tiles, connect the JTAG debugging equipment to the JTAG ICE port on the EB and the JTAG signals will be routed through any connected tiles.

The JTAG debug and configuration paths are described in JTAG support.

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