3.3. Clocks

The CT-R4F provides the five external clocks for the ARM Cortex-R4F test chip. Four of the clocks are generated locally and one is selected from one of two clocks sourced from the baseboard.

The four locally generated clocks are:

REFCLK (OSC0)

This is the main reference clock for the ARM Cortex-R4F test chip which generates the internal clocks:

  • CPU_CLK, the clock for the processor core

  • ACLK, the processor system and test chip subsystem AXI clock

  • PCLK, the AXI to APB subsystem and APB debug clock.

The frequency ratio between CPUCLK, ACLK, and PCLK is determined at reset by the value of the Clock Mode field in Config Word 0x1 that is sent to the CT-R4F by the 4-wire serial configuration interface.

FBCLK_IN (OSC1)

This clock is used to deskew the ARM Cortex-R4F internal SDRAM clock, MCLK , which is independent of ACLK. It clocks the pad side of the SDRAM memory controller ASYNC bridge in the test chip.

CLCDCLK_IO (OSC2)

This clock is the CLCDCLK panel side clock for the CLCD controller. The remaining panel side clock nCLCDCLK is generated internally by the ARM Cortex-R4F test chip and is an inverted version of CLCDCLK.

TIMERCLK

This is a fixed 24MHz clock and is the reference clock for the ARM Cortex-R4F test chip timer.

The clock sourced externally by the baseboard is:

OC_ACLK_IN

This clock is used to deskew the ARM Cortex-R4F test chip internal AXI clock, ACLK. The clock is selected from one of two sources, CLK_NEG_UP_IN or CLK_IN_MINUS1 from the baseboard. CLK_IN_MINUS1 is selected by the ARM Cortex-R4F PLD default image. This clock is exported as CLK_POS_DN_OUT to the baseboard. The generated clock, OC_AXI_CLK clocks the pad side of the ASYNC bridges on the AXI ports. This clock is exported as CLK_NEG_DN_OUT to the baseboard.

A double rate clock, OC_AXI_CLK2 is also generated by the ARM Cortex-R4F test chip and controls the AXI mux/demux operation. This clock is exported as CLK_OUT_MINUS1 to the baseboard.

A simplified diagram of the CT-R4F clocking system is shown in Figure 3.2.

Figure 3.2. CT-R4F clock system

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