Core Tile for ARM Cortex-R4F User Guide: 3.2. ARM Cortex-R4F test chip

3.2. ARM Cortex-R4F test chip

The ARM Cortex-R4F test chip is a proof-of-concept vehicle for the ARM Cortex-R4F macrocell.

The ARM Cortex-R4F test chip on the CT-R4F provides:

ARM Cortex-R4F processor implementing the ARMv7-R architecture and ARMv7 debug architecture. The test chip includes:
- A Floating Point Unit (FPU) implementing the VFPv3-D16 architecture and the Common VFP Sub-Architecture v2
- 2x 16KB L1 Caches (D and I)
- 3x 64KB TCM (A, B0 and B1)
- A Vectored Interrupt Controller (VIC) port
- A debug interface to a CoreSight Debug Access Port (DAP)
- A trace interface to a CoreSight ETM-R4 and Cross Trigger Interface (CTI).
SDRAM Controller (PL340)
Direct Memory Access Controller (PL330)
Vectored Interrupt Controller (PL192)
CLCD Controller (PL111)
High Performance Matrix (PL301)
Multiplexed Master and Slave AXI bus interfaces
Serial configuration interface
3x PLL local generators.

With the CT-R4F installed on an Emulation Baseboard (EB) it can be used for ARM Cortex-R4F benchmarking, software development, and validation. Installing a Logic Tile on the EB enables new peripherals and controllers to be developed and tested in an ARM Cortex-R4F based system.

Note

For more details see Chapter 4 Programmer’s Reference and the ARM Cortex-R4 and Cortex R4F Processor Technical Reference Manual (ARM DDI 0363).

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