3.10. JTAG support

JTAG ICE signals are present on the HDRZ header. An external baseboard provides the JTAG connector and the routing of the JTAG ICE signals from the connector to the HDRZ header. The CT-R4F routes the JTAG scan path through scan chain enabled devices on the board. The logic devices that are placed in the CT-R4F scan chain depend on the JTAG mode:

Debug mode

Debug mode is selected when the CONFIG slide-switch on the EB is set to OFF (nCFGEN is HIGH). It is the default mode used for general system development and debug. In this mode, the JTAG signals flow through the Debug Scan Chain (this scan chain connects to the ARM Cortex-R4 test chip DAP only). The JTAG signals used for debug are identified by the D_ prefix.

Configuration mode

Configuration mode is selected when the CONFIG slide-switch on the EB is set to ON (nCFGEN is LOW). This mode enables the programmable logic devices in the system to be reprogrammed. The CT-R4F reroutes the JTAG scan path to include the CT-R4F PLD, ispClock generators, and the test chip registers that are made available in the configuration scan chain. The JTAG signals used for configuration are identified by the C_ prefix.

Table 3.10 provides a description of the JTAG signals. See HDRZ signals for the JTAG pinout on the HDRZ header.

Note

In the description in Table 3.10, the term JTAG equipment refers to any hardware that can drive the JTAG signals to devices in the scan chain. Typically, RealView ICE is used for configuration and debug, although you can also use hardware from third-party suppliers to debug ARM processors.

Table 3.10. JTAG signal description

Name

Description

Function

EDBGRQ

External debug request (to CT-R4F PLD)

EDBGRQ is a request to theARM Cortex-R4F processor to enter the debug state.

DBGACK

Debug acknowledge

(to JTAG equipment)

DBGACK[3:0] indicates to the debugger that the ARM Cortex-R4F processor has entered debug state.

nCFGEN

Configuration enable

(controlled by config slide-switch on the baseboard)

nCFGEN is an active LOW signal used to put the boards into configuration mode. In configuration mode all FPGAs and PLDs that are connected to the Config Scan Chain can be configured by the JTAG equipment.

nTRST:

D_nTRST, C_nTRST

Test reset (from JTAG equipment)

This active LOW open-collector signal is used to reset the JTAG port and the associated debug circuitry on the processor. It is asserted at power-up by each module, and can be driven by the JTAG equipment. This signal is also used in configuration mode to control the programming pin (nPROG) on FPGAs.

D_nTRST is the reset for the debug mode scan chain and C_nTRST is the reset for the configuration mode scan chain.

Note

D_nTRST is always tied to D_nSRST. C_nTRST is tied to D_nTRST when configuration mode is enabled.

RTCK: D_RTCK

Return TCK

(to JTAG equipment)

Some devices sample TCK (for example a synthesizable core with only one clock), and this has the effect of delaying the time when a component actually captures data. RTCK is a mechanism for returning the sampled clock to the JTAG equipment, so that the clock is not advanced until the synchronizing device has captured the data. In a multiple device JTAG chain, the D_RTCK output from a component connects to the TCK input of the down-stream device. The RTCK signal on the EB connector HDRZ returns TCK to the JTAG equipment.

D_RTCK is the RTCK signal in the debug scan chain. RTCK is not available in the configuration mode scan chain.

TCK: D_TCK, C_TCK, SWDCLK

Test clock or SWD clock

(from JTAG equipment)

TCK synchronizes all JTAG transactions. TCK connects to all JTAG components in the scan chain. Series termination resistors are used to reduce reflections and maintain good signal integrity. TCK flows up the stack of modules and connects to each JTAG component. However, if there is a device in the scan chain that synchronizes TCK to some other clock, then all down-stream devices are connected to the RTCK signal on that component (see RTCK).

D_TCK is the clock for the debug mode scan chain and C_TCK is the clock for the configuration mode scan chain.

SWDCLK is the Serial Wire Debug (SWD) clock.

TDI: D_TDI, C_TDI

Test data in

(from JTAG equipment)

TDI goes up the stack of tiles from the baseboard (or Interface Module) and then back down the stack (as TDO) connecting to each component in the scan chain.

D_TDI is the data signal for the debug mode scan chain and C_TDI is the data signal for the configuration mode scan chain.

TDO: D_TDO, C_TDO, SWO

Test data out

(to JTAG equipment)

TDO is the return path of the data input signal TDI. For a stack of RealView products, TDI goes up to the top of the stack and returns down as TDO. The JTAG components are connected in the return path so that the length of track driven by the last component in the chain is kept as short as possible.

D_TDO is the data signal for the debug mode scan chain and C_TDO is the data signal for the configuration mode scan chain.

SWO provides Serial Wire Trace data.

TMS: D_TMS, C_TMS SWDIO

Test mode select or SWD data

(from JTAG equipment)

TMS controls transitions in the tap controller state machine. TMS connects to all JTAG components in the scan chain.

D_TMS is the control signal for the debug mode scan chain and C_TMS is the control signal for the configuration mode scan chain.

SWDIO provides bidirectional Serial Wire Debug data.


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